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Inventi Impact - VLSI

Articles

  • Inventi:evs/105/14
    A NEW APPROACH TOWARDS 32 NM FINFET BASED 4X4 SRAM CELL ARRAY USING I-BIT 6T SRAM
    Akshay Dalal, Anrav Mukharji, Ketan Machhale

    Data retention and leakage current reduction are among the major area of concern in today’s CMOS technology. A static random access memory (SRAM) is designed to plug two needs: (i) The SRAM provides as cache memory, stuck between central processing unit and dynamic random access memory (DRAM). (ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM and SRAM doesn't have need of any refresh current. Advancement of technology greatly affects the leakage current and leakage power of SRAM cell. Leakage current in memory cell is dominating factor, which is mainly impinge on the power consumption. In this paper, we've illustrated the design and implementation of FINFET based 4x4 SRAM cell array by means of one bit 6T SRAM. It has been carried out via FINFET HSPICE modeling with read and write procedure of SRAM memory.

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