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Inventi Impact - Machine Vision

Articles

  • Inventi:emv/52/14
    HARDWARE ARCHITECTURE FOR REAL-TIME COMPUTATION OF IMAGE COMPONENT FEATURE DESCRIPTORS ON A FPGA
    Abdul Waheed Malik, Benny Thörnberg, Muhammad Imran, Najeem Lawal

    This paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine vision systems demand a robust performance and power efficiency as well as minimum area utilization, depending on the deployed application. In the proposed architecture, the hardware modules for component labeling and feature calculation run in parallel. A CMOS image sensor (MT9V032), operating at a maximum clock frequency of 27MHz, was used to capture the images. The architecture was synthesized and implemented on a Xilinx Spartan-6 FPGA. The developed architecture is capable of processing 390 video frames per second of size 640 × 480 pixels. Dynamic power consumption is 13mWat 86 frames per second.

    How to Cite this Article
    CC Compliant Citation: Abdul Waheed Malik, Benny Thörnberg, Muhammad Imran, and Najeem Lawal, “Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA,” International Journal of Distributed Sensor Networks, vol. 2014, Article ID 815378, 14 pages, 2014. doi:10.1155/2014/815378. Copyright © 2014 Abdul Waheed Malik et al. This is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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