­
­
­
­

Inventi Impact - VLSI

Patent Watch

  • VLSI hot-spot minimization using nanotubes

    The invention relates to a semiconductive device comprising a die with at least one defined hot-spot area lying in a plane on the die and a cooling structure comprising nanotubes such as carbon nanotubes extending in a plane different than the plane of the hot-spot area and outwardly from the plane of the hot-spot area. The nanotubes are operatively associated with the hot-spot area to decrease any temperature gradient between the hot-spot area and at least one other area on the die defined by a temperature lower than the hot-spot area. A matrix material comprising a second heat conducting material substantially surrounds the nanotubes and is operatively associated with and in heat conducting relation with the other area on the die defined by a temperature lower than the hot-spot area. The heat conductivity of the nanotubes is greater than the heat conductivity of the matrix material, with the distal ends of the nanotubes exposed to present a distal surface comprising the first heat conducting means for direct contact with a medium comprising a cooling fluid. The inventors also disclose processes for manufacturing and using the device and products produced by the processes.

  • Method for enhancing the diagnostic accuracy of a VLSI chip

    A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.

  • Decentralised fault-tolerant clock pulse generation in VLSI chips

    The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TSAlgs exchange information between one another via a userdefined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.

  • Caching technique for electrical simulation of VLSI interconnect

    Circuits, methods, and apparatus for including interconnect parasitics without greatly increasing circuit simulation complexity and run times. Interconnect paths are reduced to one of a number of simplified topologies based on path width, length, or other parameters. The input drive waveform is similarly approximated. A grid array is formed in advance, where each point in the grid array corresponds to a set of values relating to a path topology, input waveform, and resulting output waveform. The simplified interconnect path and input waveform are mapped into a set of parameters which corresponds to a location in the predetermined grid array. The output waveform is determined by interpolating output waveforms from gridpoints surrounding the location.

  • Process for managing complex pre-wired net segments in a VLSI design

    A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

  • Content based yield prediction of VLSI designs

    An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

  • VLSI fabrication processes for introducing pores into dielectric materials

    Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.

  • Method of estimating the signal delay in a VLSI circuit

    A method estimates the signal delay in a VLSI circuit and accurately estimates the delay and conversion time of a transmission signal in the circuit in order to prevent a designer of the VLSI circuit from erroneously judging the logic made by the designed circuit.

  • Optical transceiver integratable with silicon VLSI

    A modulator for an optical transceiver is disclosed. The modulator has two quarter-wave stack mirrors composed of alternating dielectric layers with an optically absorbing layer sandwiched in between to form the vertical resonant cavity. The optically absorbing layer is made of semiconductor nanocrystals embedded in a dialectic material. The device is configured to operate near the saturation point of the absorption layer. By adjusting the biasing voltage across the absorption layer, the saturation threshold of the semiconductor nanocrystals is altered, resulting in the overall reflectivity of the resonant cavity to vary. The modulator is configured to be fabricated as the extension of the backend process of Si CMOS.

  • System and method for sign-off timing closure of a VLSI chip

    A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes.

  • Self-aligned LDMOS fabrication method integrated deep-submicron VLSI process using a self-aligned lithography etches and implant process

    An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device.

  • Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization

    A method of designing a synchronous circuit of VLSI for Clock Skew scheduling and optimization is used to optimize the skew of a digital synchronous VLSI system and formulize the issue of skew optimization into the issue of quadratic equation programming. For estimation of reliability, a quadratic equation cost function is used to analyze an ideal value of skew and an error between feasible solutions. During operation, several algorithms are used to speed up the operation and lower the complexity, and ISCAS'89 is used as a testing circuit.

  • Reducing a parasitic graph in moment computation algorithms in VLSI systems

    An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-firstsearch method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method account for coupling capacitance between interconnects.

  • Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis

    A method of estimating decaps required for an IC during an initial floorplanning design phase begins by obtaining voltage variation waveforms for a plurality of nodes in a power distribution network of the IC. Next, the method computes a minimum value for each of the voltage variation waveforms and selects voltage variation waveforms below a minimum threshold value. Following this, an FDA is performed on the voltage variation waveforms below the minimum threshold value to create a set of frequency values. This involves performing an FFT on each of the voltage variation waveforms to obtain frequency domain data, wherein frequencies that cause a drop in voltage in the plurality of nodes are filtered. The method then sorts the frequency domain data, wherein the frequency domain data is arranged in order based on amplitude value, total power, frequency components, and/or amplitude of imaginary components.

  • Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders

    A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reducedorder system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

  • Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities

    A computer implemented power optimization method that generates statistics relating to the clock gating of a set of components in a VLSI design. A set of components, including those components which are not clock gated, are identified. The generation of statistics related to clock gating testing identify whether one or more components of the set of components may be clock gated.

  • Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm

    Two-sided projection-based model reductions have become a necessity for efficient interconnect modeling and simulations in VLSI design. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the element of reduced model of the transfer function can be considered as a stopping criteria to terminate the non-symmetric Lanczos iteration process. Furthermore, the approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. The perturbation matrix only involves at most a rank-2 modification at the previous step of the non-symmetric algorithm. The information of stopping criteria will provide a guideline for the order selection scheme used in the Lanczos model-order reduction algorithm.

  • Method for hierarchical VLSI mask layout data interrogation

    The present disclosure is directed to a method for hierarchical Very Large Scale Integrated (VLSI) mask layout data interrogation. The method displays a tree diagram of the layout hierarchy and then allows the user to interrogate the mask layout shapes by using a cross probing feature.

  • Method for implementing overlay-based modification of VLSI design layout

    A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.

  • Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool

    A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method preexpands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed. The fault density value is subsequently compared to a predetermined value, wherein the predetermined value is determined using test structures and/or yield data from a target manufacturing process.

  • Buffer insertion to reduce wirelength in VLSI circuits

    Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning all sinks. The buffers are inserted at a point on a respective bounding box of a cluster that is closest to a source for the net. A sink that provides a branch connection to the buffer of another cluster is the closest sink to that buffer (except for those sinks in the cluster). Clusters may be formed by examining different pairs of the sinks with different bounding boxes, and identifying one of the pairs whose bounding box has a lowest half-perimeter as the best pair for clustering.

  • VLSI timing optimization with interleaved buffer insertion and wire sizing stages

    The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes timing comprising. Wiring layout and buffer insertion is accomplished by setting all wires in the design to an initial best possible value, inserting buffers in longest nets of wires of the design, and degrading the resulting nets. This is accomplished by a wire sizing routine which takes the nets and degrades them accordingly. This degrading is done through a combination of one or more of knocking the wires down to lower levels and reducing their thickness. The amount of degradation is dependent on the final slack.

  • Measuring and predicting VLSI chip reliability and failure

    This embodiment replaces the use of LBIST to get a pass or nopass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

  • Interpolating cubic spline filter and method

    A filter for high speed digital signal processing. In one embodiment the filter includes a linear, phase-B, interpolating cubic spline filter having a pre-filter section and an interpolating post-filter section. The pre-filter section may be formed to implement any one of a 1-4-1 cubic spline function, a 2-5-2 cubic spline function or a 1-2-1 cubic spline function. The post-filter may be formed using a plurality of running average filters arranged in a cascade (i.e., serial) fashion. The filter can be constructed using significantly fewer independent component parts for a given level of pass band and stop band performance criteria, as compared with a conventional finite impulse response (FIR) filter. The filter is thus ideally suited for implementation with very large scale integration (VLSI) technology, and in a wide variety of electronic devices where high speed digital filtering is required.

  • Silicon interposer-based hybrid voltage regulator system for VLSI devices

    A voltage regulation module and system for an integrated circuit die. The voltage regulation module includes an interposer situated in a stack between a substrate and the integrated circuit die. The interposer includes a hybrid array of voltage regulation elements for receiving voltage from the power supply and for down-converting the voltage from the power supply into a regulated voltage supplied to the integrated circuit die. The hybrid array of voltage regulation elements includes both high-bandwidth linear regulation elements for providing voltage regulation to areas on the integrated circuit die that intermittently demand relatively high current levels, and low-bandwidth switching regulator elements that are highly power efficient.

  • Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element

    Methods of fabricating a dual control gate non-volatile memory array are described. Parallel strips of floating gate material are formed over the substrate in a first direction but separated from it by a tunnel dielectric. In the gaps between these strips control gate material is formed forming a second set of parallel strips but insulated from both the adjacent floating gate stripes and the substrate. Both sets of strips are isolated in a second direction perpendicular to the first direction forming an array of individual floating gates and control gates. The control gates formed from an individual control gate strip are then interconnected by a conductive wordline such the potential on individual floating gates are controlled by the voltages on two adjacent wordlines. In other variations either the floating gates or the control gates may be recessed into the original substrate.

  • Method and apparatus for on-the-fly minimum power state transition

    The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one clock cycle. The design structure can include a netlist, which describes the VLSI circuit, reside on storage medium as a data format used for the exchange of layout data of integrated circuits, and preferably includes at least one of test data files, characterization data, verification data, or design specifications.

  • Method and apparatus for synthesis of augmented multimode compactors

    Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described. An integrated circuit has circuitry that compacts test response data from scan chains in the integrated circuit under test. In many cases groups of the scan chains are coupled to output registers, such that a same group of scan chains is coupled to sequential elements of different output registers; and the same group is a subset of the scan chains including two or more scan chains. Various computer-implemented methods divide scan chains among at least groups and partitions. The groups disallow sharing a common scan chain from the scan chains, within a particular partition. At least one common scan chain is shared between the groups of different partitions.

  • High dynamic range imaging cell with electronic shutter extensions

    A pixel sensor cell of improved dynamic range and a design structure including the pixel sensor cell embodied in a machine readable medium are provided. The pixel cell comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a "pulsed" supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation.

  • Processor architecture with wide operand cache

    A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

  • STRUCTURE AND METHOD FOR AIR GAP INTERCONNECT INTEGRATION

    Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

  • System for fext cancellation of multi-channel transceivers with precoding

    The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a novel approach is proposed to deal with FEXT interferences in the application of high/ultra-high speed Ethernet systems. Compared with the traditional FEXT cancellation approaches, the proposed FEXT canceller can deal with the non-causal part of FEXT, and thus can achieve better cancellation performance. Instead of using the conventional DFE, structure, TH precoding technique is incorporated into the proposed design to alleviate the error propagation problem. The resulting FEXT cancellers do not contain feedback loops which makes the high speed VLSI implementation easy. A modified design is also developed by using a finite signal as the input to the FEXT canceller such that the hardware complexity of the proposed FEXT canceller can be reduced.

  • STRUCTURES AND METHODS FOR AIR GAP INTEGRATION

    Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

  • Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers

    A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

  • METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE

    Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

  • Spatial Correlation-Based Estimation of Yield of Integrated Circuits

    Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2.sup.t.times.2.sup.s rectangular cells, wherein t and s are chosen so that one rectangular cell contains from about one to about five Voronoi cells. A probability of failure is computed for each of the cells in the grid. The cells in the grid are merged pairwise. A probability of failure for the merged cells is recomputed which accounts for a spatial correlation between the cells. The pairwise merge and recompute steps are performed s+t times to determine the probability of failure of the design.

  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER

    A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

  • INTERCONNECT STRUCTURES INCORPORATING AIR-GAP SPACERS

    A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

  • Rectilinear Covering Method With Bounded Number of Rectangles for Designing a VLSI Chip

    A method for creating a rectilinear non-convex polygonal output representative of a component used to build a VLSI circuit chip from a plurality of points corresponding to a plurality of components of the chip includes: covering the plurality of points with a set of rectangles; creating a Voronoi diagram for the set of rectangles; forming a nearest neighbor tree for the Voronoi diagram; connecting a selected set of the rectangles corresponding to the nearest neighbor tree into a non-convex rectilinear polygon; and applying the non-convex rectilinear polygon to build the VLSI chip.

  • CHEMICALLY AMPLIFIED RESIST COMPOSITION AND PATTERNING PROCESS

    A chemically amplified resist composition comprising a base polymer, an acid generator, and a basic compound of thiomorpholine dioxide structure has many advantages including a high contrast of alkaline dissolution rate before and after exposure, a good pattern profile after exposure, minimized roughness, and a wide focus margin. The resist composition which may be positive or negative is useful for the fabrication of VLSI and photomasks.

  • Method and system for point-to-point fast delay estimation for VLSI circuits

    The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.

  • Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions

    A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.

  • Apparatus, system, and method for enqueue prioritization

    An apparatus, system, and method are disclosed for enqueue prioritization. The apparatus for enqueue prioritization is provided with a plurality of modules configured to functionally execute the necessary steps of anticipating a need to access a computing resource, generating a dummy request, the dummy request configured to hold a place for an actual request in a queue of requests to access the computing resource, and generating an actual request to access the computing resource, wherein the actual request is configured to replace the dummy request in the queue. These modules in the described embodiments include a forecast module, a dummy generator, and a request generator.

  • Mechanisms for temporal building and parsing SIP messages

    Methods, devices, and systems for employing binary objects representing SIP messages. More specifically, a binary SIP stack is provided which allows a mechanism to enhance the efficiency of communications and more particularly to enhance the efficiency of SIP communications between SIP network elements. Also, mechanisms are provided which allow for a SIP stack to be easily and efficiently generated, transmitted over a communication network, and parsed/processed by a communication device.

  • Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits

    A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.

  • ASSESSING PRINTABILITY OF A VERY-LARGE-SCALE INTEGRATION DESIGN

    Printability of a very-large-scale integration design is assessed by: during a training phase, generating a training set of very-large-scale integration design shapes representative of a population of very-large-scale integration design shapes, obtaining a set of mathematical representations of respective shapes in the training set, identifying at least two classes of physical events causally linked to the printability for the very-large-scale integration design shapes, each of the classes being associated to a respective level of printability, labeling each mathematical representation of the set according to one of the identified classes, based on a lithography model, and selecting a probabilistic model function maximizing a probability of a class, given the set of mathematical representations; and during a testing phase, providing a very-large-scale integration design shape to be tested, testing the provided very-large-scale integration design shape, and labeling the provided very-large-scale integration design shape according to the identified class.

  • CROSSBAR SWITCH AND RECURSIVE SCHEDULING

    A crossbar switch has N input ports, M output ports, and a switching matrix with N.times.M crosspoints. In an embodiment, each crosspoint contains an internal queue, which can store one or more packets to be touted. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N.times.M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the now scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughout with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows.

  • SELF RECONFIGURING VLSI ARCHITECTURES FOR UNKNOWN SECRET PHYSICAL FUNCTIONS BASED CRYPTO SECURITY SYSTEMS

    This invention describes the use of the features of modern reconfigurable and self-reconfigurable VLSI technology to design highly secure unknown and secret physical functions for security applications. Several examples of sample implementation scenarios for self-generated secret hard-wired cipher- and/or hash functions architectures are shown. A designed, true-random, electronic mutation process autonomously activates the creation of such secret unknown functions in a self-reconfiguring VLSI architecture. It is also shown that such mutation processes can be designed to evolve dynamically in a non-predictive manner to come up with highly secure physical security mechanisms and protocols. This self-evolving property of such functions offers a great security quality which can enhance the security and identification resilience of electronic units to levels similar to those only available in biological systems with highly accurate DNA identification and secured history tracing of living entities. The invention shows also that such unknown physical functions can be used to implement highly secure cryptographic protocols which were not possible before the availability of self-reconfiguring VLSI technology. The invention description shows also how to make use of unknown tamper-proof and secret physical mapping as hash functions and ciphers even if the exact architecture is not known to anybody. A primitive identification scenario with its core protocol using an unknown secret cipher is also described, offering high security stability and resilience.

  • Hardware security module and debugging method of such a module

    The present invention relates to the field of debugging of compiled programs in a hardware security module such as a microprocessor card. A module according to the invention includes a microprocessor and a compiled program to be executed by the microprocessor in order to carry out an operation. The compiled program includes at least one debugging instruction which whether or not it is executed does not modify the execution of the operation. And, the hardware security module includes an element of inhibiting or activating the debugging instruction during the execution of the compiled program.

  • Method and apparatus for scheduling the issue of instructions in a microprocessor using multiple phases of execution

    A microprocessor configured to execute programs divided into discrete phases, comprising: a scheduler for scheduling program instructions to be executed on the processor; a plurality of resources for executing programming instructions issued by the scheduler; wherein the scheduler is configured to schedule each phase of the program only after receiving an indication that execution of the preceding phase of the program has been completed. By splitting programs into multiple phases and providing a scheduler that is able to determine whether execution of a phase has been completed, each phase can be separately scheduled and the results of preceding phases can be used to inform the scheduling of subsequent phases.

  • HARD DISK DRIVE

    A hard disk drive includes an interface, a data process system, a memory unit, a microprocessor, and an indicator module. The interface is connected to a computer for data transmission. The data process system is connected between the interface and the memory unit for reading data to or writing data from the memory unit. The microprocessor is connected with the interface for determining the status of the hard disk drive and controls the operation modes of the indicator module for illustrating whether the hard disk drive is exchanging data with the computer or whether the hard disk drive is in a fault condition.

  • ELECTRONIC CONDENSATE OVERFLOW SWITCH

    A non-polarized electronic condensate overflow switch uses microprocessor-controlled low-resistance MOSFETs to connect and disconnect power to an HVAC system. The condensate overflow switch derives operational power directly from an AC main and does not need an external power supply or a separate, reference ground line, and therefore does not require configuration in a particular polarity. The microprocessorcontrols the turning on and off of the power MOSFETs as needed when condensate overflow is detected and also provides more efficient sensing of condensate overflow and other operations, thus minimizing the power needed by the condensate overflow switch. Such a non-polarized electronic condensate overflow switch may be installed within a drain pan, in line with an outlet of the drain pan, or at a remote location away from the drain pan.

  • UNIVERSAL WIRELESS TRANSCEIVER

    A wireless transceiver includes a microprocessor for processing signals and communication circuitry coupled to the microprocessor. The communication circuitry includes input/output circuitry for receiving signals from a plurality of wireless devices over a wireless communication path, for providing the signals to the microprocessor, and for transmitting processed signals from the microprocessor to the plurality of wireless devices. The input/output circuitry of the transceiver includes a non-wireless connection coupling the wireless transceiver to a test and measurement device. The test and measurement device receives the processed signals from themicroprocessor, processes the received signal and data and/or information encoded therein, and performs a predetermined response thereto.

  • Biosensor Interface Apparatus for a Mobile Communication Device

    A bio sensor interface apparatus that utilizes pre-existing or standard electrical connectors of mobile devices such as smart phones, mobile media players, and tablets. The interface device transforms the input bio sensor signals to compatible electrical signals for input to one or more of the mobile's connectors. That signals are then conducted via one or more input conductors in the connectors to the mobile's microprocessor, which may display or transmit the biosensor signals and derive further measurements from them.

  • REMOTE CONTROL FOR ELECTRONIC DEVICE AND SIGNAL TRANSMISSION METHOD THEREOF

    A remote control for an electronic device comprises an input unit for generating control signals, a connector and a microprocessor. A connector with a plurality of interfaces, one end of connector is electrically connected to a transmission unit of the remote control via a data bus, each of the interfaces of the connector is configured for engaging with an interface of the electronic device for transmitting the control signals to the electronic device. The microprocessor determines which interface to transmit the control signals to the electronic device to control the electronic device to flip pages. A signal transmission method applied in a remote control for an electronic device is also provided.

  • Lighting Apparatus

    A lighting assembly having a socket adaptor and a microprocessor for receiving user input and selectively actuating at least one LED based on that user input. The microprocessor is electrically connected to the socket adaptor. A processor-readable medium is in electrical communication with the microprocessor. An LED assembly comprising at least one plurality of LEDs is electrically connected to the microprocessor. A lens encloses the LED assembly and the microprocessor. An input device is electrically connected to the microprocessor to receive user input.

  • SPRINKLER WATER SAVING SYSTEM

    A sprinkler water saving system comprising: a water collector, wherein said collector includes a tray to collect a specified amount of rainwater; a neck attached beneath said tray; a base situated beneath said neck to support said tray, where said base is attached to a stationary outdoor structure to enable said tray to collect said specified amount of rainwater; and a sensor within said water collector to send a signal when said tray collects said specified amount of rainwater; and a controller, where said controller activates and deactivates a sprinkler system, based upon the status of the water collector; a plurality of components attached to said controller; and amicroprocessor within said controller to operate said plurality of components, said microprocessor transmits signals for the activation and deactivation of the sprinkler system.

  • FUEL MANAGEMENT SYSTEM FOR VARIABLE ETHANOL OCTANE ENHANCEMENT OF GASOLINE ENGINES

    Fuel management system for efficient operation of a spark ignition gasoline engine. Injectors inject an anti-knock agent such as ethanol directly into a cylinder of the engine. A fuel management microprocessor system controls injection of the anti-knock agent so as to control knock and minimize that amount of the anti-knock agent that is used in a drive cycle. It is preferred that the anti-knock agent is ethanol. The use of ethanol can be further minimized by injection in a non-uniform manner within a cylinder. The ethanol injection suppresses knock so that higher compression ratio and/or engine downsizing from increased turbocharging or supercharging can be used to increase the efficiency of the engine.

  • Method of Playing a Casino Game

    A method of playing a casino game is played in conjunction with common casino table games. The game employs two identical dice and a third different colored dice called the "Dragon's Eye". Wagers are placed on the cumulative numbers of the thrown dice and on the "Dragon's Eye". A unique casino table into which wager sensors and indicator lights are imbedded, is used to facilitate the measurement and calculation of wagers and game results. Game activity data is inputted into a microprocessor and processed to identify winning wagers. The game is designed to be played at any number of casino tables prior to the play of the primary casino game. Tables are linked electronically to establish a progressive jackpot. This results in players both playing against the dealer and other players to see who wins the bonus, and against other tables to see who hits the interlinked jackpot first.

  • Method and Apparatus for Sorting Materials According to Relative Composition

    Disclosed herein is a metal sorting device including an X-ray tube, a dual energy detector array, a microprocessor, and an air ejector array. The device senses the presence of samples in the x-ray sensing region and initiates identifying and sorting the samples. After identifying and classifying the category of a sample, at a specific time, the device activates an array of air ejectors located at specific positions in order to place the sample in the proper collection bin.

  • METHODS, APPARATUS, AND SYSTEMS FOR SECURE DEMAND PAGING AND OTHER PAGING OPERATIONS FOR PROCESSOR DEVICES

    DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.

  • SYSTEMS AND METHODS FOR SYNTHESIZING HIGH RESOLUTION IMAGES USING SUPER-RESOLUTION PROCESSES

    Systems and methods in accordance with embodiments of the invention are disclosed that use super-resolution (SR) processes to use information from a plurality of low resolution (LR) images captured by an array camera to produce a synthesized higher resolution image. One embodiment includes obtaining input images using the plurality of imagers, using a microprocessor to determine an initial estimate of at least a portion of a high resolution image using a plurality of pixels from the input images, and using a microprocessor to determine a high resolution image that when mapped through the forward imaging transformation matches the input images to within at least one predetermined criterion using the initial estimate of at least a portion of the high resolution image. In addition, each forward imaging transformation corresponds to the manner in which each imager in the imaging array generate the input images, and the high resolution image synthesized by the microprocessor has a resolution that is greater than any of the input images.

  • SYSTEMS AND METHODS FOR DYNAMIC MOSFET BODY BIASING FOR LOW POWER, FAST RESPONSE VLSI APPLICATIONS

    Systems and methods in accordance with embodiments of the invention are disclosed that include MOSFET transistor operation by adjusting V.sub.bs, or the voltage applied to the body terminal of the MOSFET transistor, to control the threshold voltage (V.sub.th) in order to minimize leakage current and increase response time. One embodiment includes a n-channel metal-oxide-semiconductor field-effect transistor (NMOS), including: a gate terminal; a source terminal; a drain terminal; a body terminal; and control circuitry, where the control circuitry is configured to bias the body terminal at a first voltage when voltage applied to the gate terminal turns the transistor OFF and a second voltage when voltage applied to the gate terminal turns the transistor ON; and where the first voltage is of a lower value than the second voltage.

  • Compiler for Closed-Loop 1xN VLSI Design

    Embodiments that design integrated circuits using a 1.times.N compiler in a closed-loop 1.times.N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1.times.N building blocks. The embodiments may alter elements of the 1.times.N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1.times.N building block elements.

  • Compiler for Closed-Loop 1xN VLSI Design

    Embodiments that design integrated circuits using a 1.times.N compiler in a closed-loop 1.times.N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1.times.N building blocks. The embodiments may alter elements of the 1.times.N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1.times.N building block elements.

  • Method and System for Generating a Placement Layout of a VLSI Circuit Design

    A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.

  • METHOD FOR ESTIMATING THE LIFESPAN OF A DEEP-SUB-MICRON INTEGRATED ELECTRONIC CIRCUIT

    A large range of commercial VLSI Deep Submicron circuits are used in aeronautics for designs of electronic cards. Due to miniaturization, a continually increasing level of integration and the use of new materials in the foundries, the main failure mechanisms change whilst other ones appear. The lifetimes linked to these failure mechanisms are suspected of being shorter and shorter, so that predicting the lifetime becomes a significant challenge for the reliability of Deep Submicron (DSM) semiconductors. A new approach is proposed here, based on analyzing the technology so as to determine the potential risks to reliability with respect to the specific use of DSM components for avionics applications.

  • VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation

    VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. The VLSI layouts with spacial locality exploitation presented are applicable to generalized multi-stage and pyramid networks, generalized folded multi-stage and pyramid networks, generalized butterfly fat tree and pyramid networks, generalized multi-link multi-stage and pyramid networks, generalized folded multi-link multi-stage and pyramid networks, generalized multi-link butterfly fat tree and pyramid networks, generalized hypercube networks, and generalized cube connected cycles networks for speedup of s.gtoreq.1. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.

  • HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE

    Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.

  • SYSTEMS AND METHODS FOR DYNAMIC MOSFET BODY BIASING FOR LOW POWER, FAST RESPONSE VLSI APPLICATIONS

    Systems and methods in accordance with embodiments of the invention are disclosed that include MOSFET transistor operation by adjusting V.sub.bs, or the voltage applied to the body terminal of the MOSFET transistor, to control the threshold voltage (V.sub.th) in order to minimize leakage current and increase response time. One embodiment includes a n-channel metal-oxide-semiconductor field-effect transistor (NMOS), including: a gate terminal; a source terminal; a drain terminal; a body terminal; and control circuitry, where the control circuitry is configured to bias the body terminal at a first voltage when voltage applied to the gate terminal turns the transistor OFF and a second voltage when voltage applied to the gate terminal turns the transistor ON; and where the first voltage is of a lower value than the second voltage.

  • Optimized Semiconductor Packaging in a Three-Dimensional Stack

    A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

  • METHOD FOR AIR GAP INTERCONNECT INTEGRATION USING PHOTO-PATTERNABLE LOW K MATERIAL

    Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

  • SEMICONDUCTOR DEVICES HAVING NANOCHANNELS CONFINED BY NANOMETER-SPACED ELECTRODES

    Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.

  • CROSSBAR SWITCH AND RECURSIVE SCHEDULING

    A crossbar switch has N input ports, M output ports, and a switching matrix with N.times.M crosspoints. In an embodiment, each crosspoint contains an internal queue, which can store one or more packets to be touted. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N.times.M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the now scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughout with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows.

  • APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTS

    The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

  • CARBON NANOTUBE CROSSBAR BASED NANO-ARCHITECTURE

    Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next generation VLSI circuits. A CNT crossbar based nano-architecture, includes layers of orthogonal carbon nanotubes with electrically bistable and charge holding molecules at each crossing, forming a dense array of reconfigurable double gate carbon nanotube field effect transistors (RDG-CNFETs) and programmable interconnects, which is addressed via a voltage controlled nanotube addressing circuits on the boundaries.

  • Optimized Semiconductor Packaging in a Three-Dimensional Stack

    A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

  • METHOD FOR AIR GAP INTERCONNECT INTEGRATION USING PHOTO-PATTERNABLE LOW K MATERIAL

    Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

  • CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL ROUTING

    Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

  • MANUFACTURING PROCESS PRIORITIZATION

    A manufacturing process prioritization system. In one embodiment, the system includes at least one computing device adapted to prioritize a very large scale integration (VLSI) process, by performing actions including: querying a database for task-based data associated with a set of manufacturing tasks; applying at least one rule to the task-based data to prioritize a first one of the set of manufacturing tasks over a second one of the set of manufacturing tasks; and providing a set of processing instructions for processing a manufactured product according to the prioritization.

  • HYBRID SUBSTRATELESS DEVICE WITH ENHANCED TUNING EFFICIENCY

    In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100.times. relative to an optical device with an intact substrate, and by 5.times. relative to an optical device in which the substrate has only been removed in proximity to the optical device.

  • CARBON NANOTUBE CROSSBAR BASED NANO-ARCHITECTURE

    Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next generation VLSI circuits. A CNT crossbar based nano-architecture, includes layers of orthogonal carbon nanotubes with electrically bistable and charge holding molecules at each crossing, forming a dense array of reconfigurable double gate carbon nanotube field effect transistors (RDG-CNFETs) and programmable interconnects, which is addressed via a voltage controlled nanotube addressing circuits on the boundaries.

  • APPARATUS AND METHOD FOR MEASURING DEGRADATION OF CMOS VLSI ELEMENTS

    The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.

  • SYSTEM AND METHOD FOR GENERATING A CLOCK GATING NETWORK FOR LOGIC CIRCUITS

    A system and method for generating a power efficient clock gating network for a Very Large Scale Integration (VLSI) circuit. Statistical analysis is performed upon the activity of component registers of the circuit and registers having correlated toggling behavior are clustered into sets and provided with common clock gaters. The clock gating network may be generated independently from the logical structure of the circuit.

  • DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS

    A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained.

  • IDENTIFICATION OF INTEGRATED CIRCUITS

    Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

  • METHODS AND SYSTEMS FOR FABRICATING INTEGRATED CIRCUITS WITH LOCAL PROCESSING MANAGEMENT

    Methods and systems for fabricating integrated circuits are provided. In an embodiment, a method for fabricating integrated circuits includes hosting process recipes on a recipe management system (RMS). Processes are performed according to the process recipes on substrates with equipment units. Movement of substrates to and from equipments units is controlled with a local storage controller. A real time dispatcher (RTD) establishes a priority for processes on substrates. Further, a manufacturing execution system (MES) supervises locations of substrates and processes to be performed. Information is communicated to a local scheduler from the RMS, from each equipment unit, from the local storage controller, from the RTD, and from the MES. Based on the information, the local scheduler schedules movement of the substrates to and from the equipment units.

  • METHODS FOR FABRICATING INTEGRATED CIRCUITS USING TAILORED CHAMFERED GATE LINER PROFILES

    Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal.

  • METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH NARROW, METAL FILLED OPENINGS

    Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

  • SUB-CIRCUIT MODELS WITH CORNER INSTANCES FOR VLSI DESIGNS

    An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

  • Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Transistor

    A vertical DMOS device implements one or more deep silicon via (DSV) plugs, thereby significantly reducing the layout area and on-resistance (RDS.sub.ON) of the device. The DSV plugs extend through a semiconductor substrate to contact a conductively doped buried diffusion region, which forms the drain of the vertical DMOS device. Methods for fabricating the vertical DMOS device are compatible with conventional sub-micron VLSIprocesses, such that the vertical DMOS device can be readily fabricated on the same integrated circuit as CMOS devices and analog devices, such as lateral double-diffused MOS (LDMOS) devices.

  • SEMICONDUCTOR DEVICES HAVING NANOCHANNELS CONFINED BY NANOMETER-SPACED ELECTRODES

    Semiconductor devices having integrated nanochannels confined by nanometer spaced electrodes, and VLSI (very large scale integration) planar fabrication methods for making the devices. A semiconductor device includes a bulk substrate and a first metal layer formed on the bulk substrate, wherein the first metal layer comprises a first electrode. A nanochannel is formed over the first metal layer, and extends in a longitudinal direction in parallel with a plane of the bulk substrate. A second metal layer is formed over the nanochannel, wherein the second metal layer comprises a second electrode. A top wall of the nanochannel is defined at least in part by a surface of the second electrode and a bottom wall of the nanochannel is defined by a surface of the first electrode.

  • GRAPH BISECTION

    Techniques are described for graph partitioning, and in particular, graph bisection. A lower bound is provided that is computed in near-linear time. These bounds may be used to determine optimum solutions to real-world graphs with many vertices (e.g., more than a million for road networks, or tens of thousands for VLSI and mesh instances). A packing lower bound technique determines lower bounds in a branch-and-bound tree, reducing the number of tree nodes. Techniques are employed to assign vertices without branching on them, again reducing the size of the tree. Decomposition is provided to translate an input graph into less complex subproblems. The decomposition boosts performance and determines the optimum solution to an input by solving subproblems independently. The subproblems can be solved independently using a branch-and-bound approach to determine the optimum bisection.

  • SIGNATURE COMPRESSION REGISTER INSTABILITY ISOLATION AND STABLE SIGNATURE MASK GENERATION FOR TESTING VLSI CHIPS

    A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the one or more save and restoring LFSR registers upon reaching a predetermined number of test loops; performing a signature stability test by loading said initial seed to said LFSR, executing the predetermined number of BIST test loops, and comparing the resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register.

  • ACCELERATOR FOR A READ-CHANNEL DESIGN AND SIMULATION TOOL

    A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.

  • METHODS FOR FORMING A SEALED LIQUID METAL DROP

    Methods for forming an enclosed liquid metal (LM) drop inside a sealed cavity by formation of LM components as solid LM component layers and reaction of the solid LM component layers to form the LM drop. In some embodiments, the cavity has boundaries defined by layers or features of a microelectronics (e.g. VLSI-CMOS) or MEMS technology. In such embodiments, the methods comprise implementing an initial microelectronics or MEMS process to form the layers or features and the cavity, sequential or side by side formation of solid LM component layers in the cavity, sealing of the cavity to provide a closed space and reaction of the solid LM components to form a LM alloy in the general shape of a drop. In some embodiments, nanometric reaction barriers may be inserted between the solid LM component layers to lower the LM eutectic formation temperature.

  • DENSITY-BASED INTEGRATED CIRCUIT DESIGN ADJUSTMENT

    The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

  • METHOD FOR ADJUSTING A LAYOUT OF AN INTEGRATED CIRCUIT

    A method for adjusting a layout of an integrated circuit includes a first layer, a second layer, a target metal line, and a first non-target metal line. The integrated circuit is configured for a focused ion beam (FIB) detection to the target metal line. The method includes the steps of: disposing the first non-target metal line on the first layer; disposing the target metal line on the second layer; and adjusting one of the target metal line and the first non-target metal line such that the target metal line can be detected by the FIB detection.

  • METHOD AND APPARATUS OF PROVIDING SIM PROFILE FOR EMBEDDED UNIVERSAL INTEGRATED CIRCUIT CARD

    There are provided a method of providing a SIM profile to an eUICC device online and a device using the same. The method of providing the SIM profile includes purchasing the SIM profile provided in an app store using a user device capable of accessing the app store, downloading the purchased SIM profile in the eUICC device using the eUICC device capable of accessing the app store, and installing the SIM profile, that is downloaded in the eUICC device, in the eUICC device therein. Therefore, it is possible to purchase the SIM profile using the online app store that is operated in a variety of forms and easily install the purchased SIM profile in the eUICC device.