In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode.
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications
The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes.
A system and method for securing communications between a plurality of users communicating over an optical network. The system utilizes a fixed or tunable source optical generator to generate entangled photon pairs, distribute the photons and establish a key exchange between users. The distribution of entangled photon pairs is implemented via at least one wavelength selective switch.
The present subject matter relates to systems and methods for assortment planning and optimization in a retail environment. In one implementation, a method for assortment planning and optimization is described. The method includes receiving assortment parameter data, and input information. The input information includes performance data, product data, fixture data and store data. Further, the method includes ranking product items based at least on the assortment parameter data and the input information. Furthermore, the method includes creating a listing of the product items based at least on the ranking. Such listing of the product items is processed based at least on predefined business rules, to generate one or more assortment solutions for providing optimal gross margins.
A method for providing an automatically reconfigurable input interface includes analyzing input received through an input interface of the computing device, determining a context based on the input; and reconfiguring the input interface to comprise a key based on a domain associated with the context. A computing system for providing automatic reconfiguration of an input interface includes a processor and a memory communicatively coupled to the processor. The processor is configured to analyze input received through an input interface of a computing device, determine a context based on the input, and reconfigure the input interface to comprise a key based on a domain associated with the context
A method for providing an automatically reconfigurable input interface includes analyzing input received through an input interface of the computing device, determining a context based on the input; and reconfiguring the input interface to comprise a key based on a domain associated with the context. A computing system for providing automatic reconfiguration of an input interface includes a processor and a memory communicatively coupled to the processor. The processor is configured to analyze input received through an input interface of a computing device, determine a context based on the input, and reconfigure the input interface to comprise a key based on a domain associated with the context.
Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.
The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
Provided are a computing apparatus and method based on SIMD architecture capable of supporting various SIMD widths without wasting resources. The computing apparatus includes a plurality of configurable execution cores (CECs) that have a plurality of execution modes, and a controller for detecting a loop region from a program, determining a Single Instruction Multiple Data (SIMD) width for the detected loop region, and determining an execution mode of the processor according to the determined SIMD width.
The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31') that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.
Some embodiments of the invention relate to a DC offset correction circuit comprising a feedback loop having a DAC controlled by a reconfigurable ADC, which determines (e.g., tracks) the mean value of a modulated input signal. The circuit operates according to two phase process. In a first \"pre-modulation\" tracking phase, an input signal is tracked by the ADC, which is configured to output the input signal's mean value as a digital code equivalent to the input mean value. The output of the ADC is provided to a DAC, which provides an analog representation of the mean value to an adder that subtracts the mean value from the modulated input signal to generate a bipolar adjusted input signal. In a second \"modulation\" phase, the estimated mean value is held constant, so that the bipolar adjusted input signal may be provided to an activated modulation circuit for improved system performance.
The present disclosure is a novel utility of a software defined radio (SDR) based Distributed Antenna System (DAS) that is field reconfigurable and support multi-modulation schemes (modulation-independent), multi-carriers, multi-frequency bands and multi-channels. More specifically, the present invention relates to a DAS utilizing one or more Daisy-Chained Rings of Remote Units. The present invention enables a high degree of flexibility to manage, control, enhance, facilitate the usage and performance of a distributed wireless network such as Flexible Simulcast, automatic traffic load-balancing, network and radio resource optimization, network calibration, autonomous/assisted commissioning, carrier pooling, automatic frequency selection, frequency carrier placement, traffic monitoring, traffic tagging, pilot beacon, etc. As a result, a DAS in accordance with the present invention can increase the efficiency and traffic capacity of the operators' wireless network.
The present invention extends to methods, systems, and computer program products for delivering customer specified receipt types at checkout. A customer specifies receipt delivery preferences at a mobile device (e.g., specifying delivery of a digital receipt and/or a paper receipt at checkout). The mobile device sends the customer's receipt delivery preferences to a receipt preferences database server for storage in a receipt preferences database. During a sales transaction, a point-of-sale (\"POS\") system refers to the receipt preferences database (or a relevant portion thereof) to access the customer's receipt delivery preferences. Based on the customer's receipt delivery preferences, the point-of-sale (\"POS\") system delivers appropriate types of receipts (e.g. digital and/or paper) to the customer.
A method of dynamically reconfiguring a distributed computing architecture having a plurality of processing nodes, where each processing node hosts a respective plurality of virtual machines, includes detecting a fault condition on a first processing node, assessing the criticality of a software function performed by each of the respective virtual machines on the first processing node, and reassigning at least one of the plurality of virtual machines on the first processing node to a second processing node if the at least one virtual machine is deemed critical.
A reconfigurable doll includes a body having a torso defining a cavity, and a garment member coupled to the body. The garment member is movable between an extended position extending outwardly from the torso, and a retracted position substantially disposed within the cavity.
Apparatus and methods for a bilinear filter system comprising a pre-formatter module, a bilinear module, an accumulator module, and a format module. The pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format. The bilinear module is dynamically reconfigurable to perform an interpolation or an extended precision interpolation on the normalized fixed point texel data from the pre-formatter module and generate re-normalized floating point texel data. The interpolator analyzes the exponent range of fixed point texel data from the pre-formatter module to determine if an extended precision calculation is appropriate. The accumulator module is configured to accumulate floating point texel data from the bilinear module to achieve the desired level of bilinear, trilinear, and anisotropic filtering. The format module is configured to convert texel data from the accumulator module into a standard floating point representation.
Embodiments of the invention are directed towards scalable and dynamically configurable (and reconfigurable) device host controller solutions for system platform controller hubs (PCH). Embodiments of the invention may include logic or modules to detect a device coupled to a common I/O port (alternatively referred to as a converged I/O port) of a host system and determine its device type. Said logic or modules may further load host controller firmware for the device type from a memory to a processing core, such that the processing core will execute the host controller firmware to enable data transfer between the device and the host system. Said processing core may be configured and reconfigured based on the device type connected to the associated common I/O port.
A dynamically reconfigurable processor which executes a series of processes on an instruction basis for respective instructions, comprises: a dynamically configurable computing unit; and a clock generating circuit, wherein start timing for processes in the series of processes is determined based on the main clock except for an instruction execution process of executing the instruction with the dynamically configurable computing unit, the instruction execution process of executing the instruction with the dynamically configurable computing unit includes a computing element generating sub-process of dynamically configuring, with dynamically configurablecomputing unit, a computing element corresponding to the instruction, and an operation sub-process of performing an operation according to the instruction with the computing element configured in the computingelement generating sub-process, start timing for the computing element generating sub-process and the operation sub-process is determined based on the sub-clock, and the sub-clock is generated such that thecomputing element generating sub-process and the operation sub-process are completed before the start timing for a process which is to be executed immediately after the instruction execution process.
Generalized learning rules may be implemented. A framework may be used to enable adaptive signal processing system to flexibly combine different learning rules (supervised, unsupervised, reinforcement learning) with different methods (online or batch learning). The generalized learning framework may employ average performance function as the learning measure thereby enabling modular architecture where learning tasks are separated from control tasks, so that changes in one of the modules do not necessitate changes within the other. Separation of learning tasks from the control tasks implementations may allow dynamic reconfiguration of the learning block in response to a task change or learning method change in real time. The generalized learning apparatus may be capable of implementing several learning rules concurrently based on the desired control application and without requiring users to explicitly identify the required learning rule composition for that application.
A functional logic block for embedding into a reconfigurable array, the functional logic block comprises at least one multi-bit register including a plurality of single-bit registers, the single-bit registers being divided into at least two groups. The functional logic block also comprises a shift chain for connecting each group of single-bit registers, each shift chain being arranged to connect its respective group of single-bit registers into a configuration and test chain.
An apparatus and a method for processing debugging trace data for a reconfigurable computing apparatus take advantage of a first mode and a second mode of the reconfigurable computing apparatus being mutually exclusive, wherein first instructions associated with a loop operation are executed in the first mode, and second instructions associated with a general operation other than the loop operation that can be processed in parallel are executed in the second mode, so that, without the need for an additional memory, debugging trace data can be efficiently stored using a first memory configured to store configuration information for use in configuring a connection path between processing elements arranged in a reconfigurable unit in the first mode, and a second memory from which an instruction word including a plurality of the second instructions is fetched in the second mode.
Flexibly configurable button panels for electronic devices and dynamic display systems for wager based gaming machines are disclosed. Button panels include a flexible cable, surface mount or other cable connectors spaced along and coupled thereto, and button assemblies coupled thereto via the cable connectors to provide electrical access from buttons to circuit lines. Relative physical locations of buttons are then reconfigurable to form different button panel configurations while the buttons remain coupled to the flexible cable. A dedicated dynamic button panel controller for processing button functions and a button panel identification device having an identification code can also be provided. Buttons can be removably coupled to the cable connectors, and can also include dynamic displays thereupon. Other gaming machine dynamic displays can also be provided. Separate dynamic display controllers can be provided to control dynamic displays directly to alleviate processing burdens on the master gaming controller.
The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC.
A remote radio head unit (RRU) system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier inside the RRU. The power amplifier characteristics such as variation of linearity and asymmetric distortion of the amplifier output signal are monitored by a wideband feedback path and controlled by the adaptation algorithm in a digital module. Therefore, embodiments of the present invention can compensate for the nonlinearities as well as memory effects of the power amplifier systems and also improve performance, in terms of power added efficiency, adjacent channel leakage ratio and peak-to-average power ratio. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers, multi-frequency bands and multi-channels. As a result, the remote radio head system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems.
In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The present invention is further configured to enable processing core and memory utilization by external systems through virtualization.
Various embodiments of the present invention are directed to image viewing systems. In one aspect, an image viewing system includes a projection system (104, 504, 604), and a dynamically reconfigurable screen (102, 502, 602). The projection system projects two or more images of perspective views of objects or a scene onto the screen. The screen is dynamically reconfigured to separately reflect each image to an associated viewing zone, enabling a viewer looking at the screen to the view the objects or the scene from different viewing zones.
A chip having an intelligent fabric may include a soft application processor, a reconfigurable hardware intelligent processor, a partitioned memory storage, and an interface to an external reconfigurable communication processor. The reconfigurable hardware intelligent processor may be configured to implement a distributed reconfigurable processor, and to provide cognitive control for at least one of allocation, reallocation, and performance monitoring.
An interactive retail shopping system includes one or more computing devices and a date store operatively coupled to the computing devices. Each of the computing devices includes a processor, memory operatively coupled to the processor and a display device operatively coupled to the processor for exhibiting data and information thereon. The data store includes data and information defining an inventory of merchandise. Each of the processors execute computer implemented instructions that allow consumers to locate, to review and to select merchandise from within the inventory of merchandise, and that allow a retailer to pick and to present the selected merchandise and alternative merchandise to the consumers for purchase within a retail shopping environment.
A layered architecture for customer payload systems is disclosed to provide a scalable, reconfigurable integration platform targeted at multiple unmanned aerial vehicles (UAV), and remove both UAV specific and payload equipment specific characteristics that increase complexity during integration. The layered architecture is a modular design architecture that is split by function. Standard interfaces are implemented between functional layers to increase reconfiguration possibilities and to allow reuse of existing components and layers without modification to the payload or UAV. The standard interfaces also promote easy connection and disconnection from other layer components. Additionally, once the layered architecture is implemented, technological or functional requirements changes can be isolated to one specific component layer, not the entire payload stack. As a result, payload designs based on the layered architecture reduces design time and cost, and allows for easier integration, operation, upgrades, maintenance, and repair.
A product dispenser reconfigurable in the field includes a housing, at least one tower unit, and a removable ambient box. The at least one tower unit includes at least one dispense point, whereby a product or diluent is delivered from a diluent or product source to the dispense point. The ambient box is an insulated product path that is adaptable to at least one external source and the tower units or the dispense points. The external source may be conditioned through external means or may deliver an ambient temperature product, wherein the product circuits passing through the ambient box may deliver product to any tower unit, thereby providing increased product variability within a same product dispenser. The product dispenser still further includes a tower structure that is removable without disabling the product circuits, and a method of merchandising on the tower structure.
A method and apparatus for approaches for troubleshooting optical networks, particularly ROADM-based networks is described. The method includes designating a first port, of an optical communication node of a transport network, as an ingress for a loop-back optical signal to troubleshoot the transport network, designating a second port, of the optical communication node, as an egress for the loop-back optical signal, and establishing a loop-back connection between the first port and the second port to transport the loop-back optical signal.
A transmit antenna pattern is provided. A method for determining the transmit antenna pattern includes determining first Signal to Interference and Noise Power Ratios (SINRs) of a first mobile station and a second mobile station based on first Channel Quality Indicator (CQI) values received from a first base station and a second base station in the first operation when a transmit antenna pattern of the first base station is fixed and a transmit antenna pattern of the second base station is changed, determining second SINRs of the first mobile station and the second mobile station based on second CQI values received from the first base station and the second base station when the transmit antenna pattern of the first base station is changed and the transmit antenna pattern of the second base station is changed, and determining a transmit antenna pattern exhibiting the best performance based on the determined SINRs.
A method and system for rapidly generating software applications is provided. An application model of a software application is generated which comprises modeled components and technology stack information. The modeled components correspond to functional and design aspects of the software application. The application model is generated by dragging and dropping multiple components into corresponding modeling perspectives defined in a visual modeling environment. Descriptors are generated for the application model which are logical representations describing each of the modeled components. Further, the descriptors are generated from application model object of the application model. Furthermore, technology templates are identified based on the technology stack information in the application model. The technology templates are predetermined templates comprising scripting languages for automatically transforming the application model into one or more technologies. Code related to the software application is generated based on the descriptors and the identified technology templates.
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions.
A method, an article of manufacture, and a process are provided for securing data sets by dynamically hopping amongst a variety of data encryption and/or manipulation protocols. Such dynamic protocol hopping can be implemented in reconfigurable logic. The encryption protocol applied to the data set is selected from among a plurality of encryption protocols. Preferably, the selection can be driven by a random number generator.
A system and method for processing electronic devices to determine removal of customer personal information (CPI). An electronic device is connected to a test device. A number of electronic devices including the electronic device are received for determining that the CPI is removed from a number of sources. The number of electronic devices include a number of makes and models of electronic devices. A determination of whether CPI is included on the electronic device is made. An identification of the electronic device is recorded in response to determining that CPI is included on the electronic device. The CPI is cleared form the electronic device in response to determining that the CPI is included on the electronic device. The identification of the electronic devices and metadata is reported in response to determining the CPI was included on the electronic device.\r\nUnited States Patent Application 20140059676\r\nKind Code A1\r\nWendling; Jean-Hugues ; et al. February 27, 2014\r\n________________________________________\r\nSYSTEMS AND METHODS FOR DUAL READER EMULATION \r\n\r\n\r\nAbstract\r\nSystems and methods for emulating credentials are disclosed. In some cases, the systems include an access credential reader and an access credential writer. The access credential reader is communicably coupled to the access credential writer. The access credential reader is operable to receive information from an access credential, and to transfer at least a portion of the information to the access credential writer. The access credential writer is operable to transfer at least the portion of the information to an emulation access credential.
A system for reconfiguring a node of a complex system health monitoring system without recompiling and relinking executable code is provided. The system includes a software module containing previously compiled instructions to perform one of a plurality of different standardized functions and a computing node comprising a processor and plurality of software objects, the processor configured to execute the previously compiled instructions. The system further includes a configuration file configured to provide static and dynamic data to the software module, the configuration file comprising a dynamic data store (DDS), a static data store (SDS) and a binary code database (BCD). The BCD comprises a library of externally compiled executable algorithms that are callable by the software module. The BCD being configured with database identification and retrieval data structures associated with library of externally compiled executable algorithms.
Methods and reconfigurable systems are provided for monitoring the health of a complex system. The reconfigurable system comprises a plurality of standardized executable application modules containing instructions to perform one of a plurality of different standardized functions. The system further comprises a plurality of computing nodes arranged in a hierarchical structure comprising one or more layers of computing nodes. Eachcomputing node of the plurality runs a host application and a workflow service module, each computing node thereby being configured by a configuration file that directs the execution of any of the standardized executable application modules in a cooperative fashion by the host application via the workflow service module. The system also comprises a loading means for populating each computing node with one or more standardized executable application modules of the plurality, a communication means, and a configuration means for programming the populated standardized executable application modules.
Disclosed herein are mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption for, inter alia, increased device battery life. The techniques disclosed herein enable greatly enhanced compression/decompression as well as encryption and decryption functionality to be provided in addition to overall greater processing capability particularly in those applications wherein minimization of power consumption is desired. Package-on-package and other assembly techniques may be used to provide the reconfigurable processor in a small footprint package.
A high performance and cost effective method of RF-digital hybrid mode power amplifier systems with high linearity and high efficiency for multi-frequency band wideband communication system applications is disclosed. The present disclosure enables a power amplifier system to be field reconfigurable and support multiple operating frequency bands on the same PA system over a very wide bandwidth. In addition, the present invention supports multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels.
In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands.
A method and system for designing and implementing a reconfigurable Doherty amplifier system are disclosed. In one embodiment, a design method includes determining, using a processor, a first set of ABCD transmission parameters of a first output compensation network in a main path of a Doherty amplifier for the case where an auxiliary amplifier of the Doherty amplifier is off. The method further includes determining, using a processor, a second set of ABCD transmission parameters of a second output compensation network in an auxiliary path of the Doherty amplifier based on the first set of ABCD transmission parameters.
A multi-user host computer system comprises processor blades combined with terminal services blades to provide acceleration and proxy server functions for supporting a variety of remote terminals. For each remote terminal, the terminal services blade and proxy server functions may improve the video and graphics performance. This allows the multi-user host computer system to more efficiently support multiple users. The terminal services blade may include a graphics processor that manages a virtual display for each remote terminal and provides selective updates of sub frame data. Where appropriate, the sub frame data is encoded and transmitted over the network to the remote terminals. The terminal services processor also offloads and optimizes video data streams for the intended remote terminals and their respective network connections. Processor blades may include a baseboard management controller that utilizes advanced features for supporting remote KVM administration.
A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
An offer redemption system is provided with least one computing device. An offer clearinghouse application is executable in the at least one computing device. The offer clearinghouse application includes, (i) one or more processes that receives details of an offer including at least one product to which n offer applies and at least one offer restriction for the offer, (ii) one or more processors that provides for distribution of the offer to users on behalf of an advertiser and (iii) one or more processors that provides for redemption of the offer with a retailer. A retailer interface receives, at a time of offer redemption, information to identify a retail transaction and line item used by an offer validation.
A peripheral component interconnect express (PCI-E) system has a reconfigurable link architecture. The system comprises a system slot adapted to receive a PCI-E compatible system controller, a plurality of peripheral slots adapted to receive a plurality of peripheral modules, and a reconfigurable switch fabric configured to create a variable number of PCI-E links between the system slot and the plurality of peripheral slots.
Embodiments are directed to aggregating product savings into a quick response (QR) code and to providing a targeted offer via a financial transaction receipt. In one scenario, a computer system scans various items that are provided for sale by a retailer. The scanning resulting in scanning information that corresponds to the scanned items. The computer system sends the scanning information for the scanned items to a second computer system to determine whether coupons or price discounts apply to the scanned items. The computer system then receives coupons or price discounts for the scanned items from the second computer system and aggregates each of the received coupons or price discounts into a QR code that is presentable by a customer at a point of sale to redeem the coupon or price discount for the scanned items.
Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit.
Reconfigurable antennas in an ad-hoc network are provided where all nodes employ MIMO/SIMO/MISO communication techniques. Three types of reconfigurable antennas: Reconfigurable Printed Dipole Array (RPDA), Reconfigurable Circular Patch Antenna (RCPA) and Two-Port Reconfigurable CRLH Leaky Wave Antennas are used. The RPDA, RCPA and the CRLH Leaky Wave antennas have a different number of configurations as well as different degrees of pattern diversity between possible configurations. To effectively use these antennas in a network, the performance of centralized and decentralized antenna configuration selection schemes are quantified for reconfiguration at one or both link ends. The sum capacity of the network is used as a metric to quantify the performance of these antennas in measured and simulated network channels.
A portable computer system is provided having a first unit with touch-sensitive LCD display screen and a detachable second unit having a keyboard. The first unit includes a support structure movable between a stowed position and a deployed position, which can support the first unit in an inclined position on a planar surface. The support structure can help support the first unit when mounted on the second unit, standing alone, or both.
A method and system for adaptively docking with computers of different designs are provided. In one version, an electrical communications connector (hereinafter, \"docking connector\") is coupled with a docking station frame, wherein the docking connector may be positioned relative to the frame. A computer having a native connector may be positioned relative to the frame, and the docking connector may be positioned relative to both the frame and the computer to permit communicative coupling of the docking connector and the native connector of the computer.
A reconfigurable computing circuit for reducing amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig computing block 2010, reg setting data selecting unit 3400 selects either a value stored in reg setting data storage unit 3000 or an initial value output from data reg data generating unit 4000, based on the information stored in reg type managing unit 1100 that indicates the types of registers and the connection order of the registers in the scan chain, and outputs the selected value in sequence to the scan chain under control of scan/reconfig control unit 1000. Each register in the scan chain then shifts data stored therein to the next register in the scan chain in sequence.
A reconfigurable computing device includes a reconfigurable logical device of which a circuit logic can be changed based on configuration data, a storage part to store beforehand input-output attributes of input-output parts of the reconfigurable logical device, and a verification part to verify the configuration data by making a comparison between information on the input-output parts in the configuration data and the input-output attributes stored in the storage part. With this, it is possible to inspect the configuration data of the reconfigurable logical device by a simple method.
Systems, methods and computer programs products for a reconfigurable data distribution system are described herein. An embodiment includes a stream generator that receives analog data from a plurality of sensors. Data received from sensors, for example, may include video data received from an externally mounted camera on an armored vehicle. The stream generator converts analog data received from the sensors into a digital format that can be transmitted to a router. The router forwards the data in the digital format to a display processor. The display processor formats the data received from the router for display on a display device. The display processor may also receive data from other peripherals, including but not limited to, a touch screen device or a keypad.
According to the present invention, in changing the circuit configuration of a reconfigurable device, a circuit configuration change period is shortened while avoiding a dependency on processing contents without increasing the size of a circuit due to addition of a mechanism. Considering an execution order relation between a plurality of data flows, a setting change count necessary for changing the circuit configuration in changing processing is decreased within a constraint range, thereby shortening the circuit configuration change period.
A reconfigurable downhole article is disclosed. The article comprises a base material. The article also comprises a removable material disposed on or within the base material that is configured for removal from the base material in response to a wellbore condition, wherein the base material and the removable material define a base article that is configured to perform a first function, and wherein upon removal of the removable material, the base material defines a modified article that is configured to perform a second function that is different than the first function.
An interchangeable cumberbund with integrated wiring to allow for connecting a variety of electronic devices for an intended purpose or mission and exchanging a configured garment for another. The reconfigurablecumberbund allows for multiple quick-disconnect cable harnesses to be weaved into the cumberbund which enables rapid and convenient removal of hardware that incorporates all I/O to a computer. The reconfigurablecumberbund connected to a wearable tactical vest containing a mobile ultra-rugged personal computer is the essential combination that allows hands-free use by the user.
Charging devices, modular adapters, and circuits are provided. One charging device including a body including a rechargeable energy storage device and a housing. The housing includes at least one first coupling portion. The charging device further includes a modular adapter including a second coupling portion configured to be mated to the first coupling portion of the housing. When mated to the housing, the modular adapter is configured to be electrically connected to the rechargeable energy storage device. When the modular adapter is mated to the housing, the body and the modular adapter form a single integrated and substantially rigid structure.
Computer-aided design and manufacture software and hardware automate garment and fashion definition and production. Configurable garment includes ornamental element, pattern display, and personal identifier and wireless sensor electronics.
The exemplary embodiments provide a reconfigurable integrated circuit capable of on-chip configuration and reconfiguration, comprising: a plurality of configurable composite circuit elements; a configuration and control bus; a memory; and a sequential processor. Each composite circuit element comprises: a configurable circuit; and an element interface and control circuit, the element interface and control circuit comprising an element controller and at least one configuration and control register to store one or more configuration and control words. The configuration and control bus is coupled to the plurality of configurable composite circuit elements, and comprises a plurality of address and control lines and a plurality of data lines. The sequential processor can write configurations to the configuration and control registers of an addressed configurable composite circuit element to configure or reconfigure the configurable circuit.
A reconfigurable integrated circuit device includes plural processing elements each including an arithmetic circuit, and being configured in any computing state based on the configuration data; and an inter-processing element network which connects the processing elements in any state based on the configuration data. And the processing element inputs an input valid signal and an input data signal, and outputs an output valid signal and an output data signal, and includes an input data holding register, an arithmetic processing circuit, and an output data holding register which holds the computing result data, and when the configuration is updated by configuration data which makes a hold mode valid, regardless of the input valid signal, valid or invalid, the input data holding register holds the input data signal upon the update and the arithmetic processing circuit performscomputing processing on the input data signal held in the input data holding register.
In one embodiment, a reconfigurable keyboard having electronically writable keys receives input signals from a configurer that, for a first setting, results in a first displayed key layout, and in a second setting, results in a second displayed key layout. Each setting is associated with a specific functionality of the keyboard, for example a particular language. A configurer operates to execute the particular layouts and functionalities, and can be disposed on a portable device such as a memory stick for use with different computers and keyboards.
A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.
Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.
An apparatus for reconfigurable computing logic implemented by an innovative memristor based computing architecture. The invention employs a decoder to select memristor devices whose ON/OFF impedance state will determine the reconfigurable logic output. Thus, the resulting circuit design can be electronically configured and re-configured to implement any multi-input/output Boolean logic computing functionality. Moreover, the invention retains its configured logic state without the application of a current or voltage source.
Methods, systems, and devices are described for providing a reconfigurable multi-chip WWAN processing platform on a communications device. The processing platform allows the device to access multiple WWANs and multiple WWAN technologies concurrently. A first multiplexer is communicatively coupled with a number of baseband processing chips. A first baseband processing chip is selectively coupled with a first transceiver and a first UICC module to establish a first connection. A second baseband processing chip is selectively coupled with a second transceiver and a second UICC module to establish a second connection operable concurrently with the first connection. A multiplexer controller performs a configurable search for available networks. One or more networks are selected. The controller selects a specific transceiver for each selected network based on the capabilities of the transceiver. Baseband processing chips that consume less power serve as proxies for other baseband processing chips that consume more power.
A reconfigurable operation apparatus includes a reconfigurable circuit, a storage unit and a control unit. The reconfigurable circuit has a plurality of small circuits and reconfigures a circuit using the small circuit selected from the plurality of small circuits based on recorded circuit information. The storage unit stores first and second circuit information which corresponds to first and second compression circuits, respectively. The control unit reconfigures the reconfigurable circuit into the first or second compression circuit by recording the first or second circuit information in the reconfigurable circuit in accordance with an input data string.
A power strip for conducting electrical power between an electrical power outlet having at least a live receptacle and a neutral receptacle, and at least two electrical device power plugs, each plug having at least a live prong and a neutral prong. The power strip includes a first housing segment having a first receptacle configured to receive at least an electrically conductive portion of a first device plug and a second housing segment having a second receptacle configured to receive at least an electrically conductive portion of a second device plug. The second housing is coupled to the first housing for pivotal movement relative to said first housing;
A reconfigurable polarity detachable connector assembly includes a housing defining two accommodation channels and providing a springy protruding member at a top side, two mating simplex connectors respectively detachably mounted in the accommodation channels of the housing, a fiber optic cable fastened to the housing with two optical fiber cores thereof respectively inserted into respective calibration support rods of the mating simplex connectors, and a sliding cap slidably coupled to the housing. The sliding cap is unlocked and can be moved backwardly relative to the housing to expose the optical fiber cores of the fiber optic cable to the outside of the housing for allowing position exchange between the two mating simplex connectors after the user presses the springy protruding member.
The present invention relates to a reconfigurable power converter module for a wind turbine facility adapted to supply electric power to an associated power supply grid. The reconfigurable power converter module comprises a frequency converter operatively connected to filter means, wherein said frequency converter and said filter means are mutually reconfigurable so as to suppress internal and/or internal resonances/harmonics.
Provided is a reconfigurable processor capable of reducing the routing processing time of routing nodes by driving the routing nodes at a greater frequency than a driving frequency of the processing elements. The reconfigurable processor includes one or more processing elements configured to be driven at a first driving frequency, and one or more routing nodes configured to be provided on paths that are formed between the processing elements, and to be driven at a second driving frequency that is greater than the first driving frequency.
An apparatus and method are provided to minimize an overhead caused by mode conversion by processing parts that cannot be subject to software pipelining. A processor is configured to execute code including a first part that is able to be subject to software pipelining in the code, and a second part that is disable to be subject to software pipelining in the code, the second part including a data part and a control part. The processor is further configured to execute the first part, and the data part of the second part in a first execution mode, and to execute the control part of the second part in a second execution mode. When the first part and the data part, the data part and the first part, or different data parts are successively executed, the processor processes the code in the first execution mode without entering the second execution mode.
Reconfigurable 3D interconnect is provided that can be used for digital and RF signals. The reconfigurable 3D interconnect can include an array of vertical interconnect vias (or TSVs) providing a signal path between a first core element of a 3D IC and a second core element of the 3D IC stacked above the first core element. A routing circuit can be used to route a signal from the first core element to the second core element through selected TSVs of the array of TSVs providing the signal path between the first core element and the second core element. The routing circuit allows re-routing of the signal through different selected TSVs during operation, which can provide real time adjustments and capacity optimization of the TSVs passing the particular signal between the elements.
A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.
A reconfigurable touch screen computing device with folding configurations and an alignment locking mechanism. The touch screen display is made up of segments coupled to a flexible circuit and can be reconfigured from a compact state to an expanded state. The form factor of the compact state is roughly the size of a typical handheld phone, with an integrated speaker and microphone. The form factor of the expanded state is roughly the size of a tablet computer which may also include the mechanical functionality of a laptop. Both states provide a configuration which includes a touch screen display on a front side and a protective housing on a back side. The computing device may further include sensors to indicate the state of configuration. In one embodiment, a module attached to, situated within, or otherwise associated with at least one segment may contain all or substantially all processing and memory, along with a communications system, all of which may be used in either state.
Methods and devices for configuring and displaying user interface elements of a multi-display device relative to a device state and/or device orientation. More particularly, the device is equipped with one or more sensors that facilitate the detectability of the relationship of the primary screen to the secondary screen and the general orientation of the device. The method includes accepting a set of user preferences for individual user interface elements for various device states and/or device orientations. The method and device may configure individual windows, per user settings, relative to device state and/or user orientation of the device. The method and device may present, for example, a single set of reconfigurable and/or re-locatable user interface elements in different locations depending on device orientation and/or display mode. Further, the method and device may provide the user the ability to switch both display mode and user interface action simultaneously.
A reconfigurable wireless modem adapter is provided. The reconfigurable wireless modem adapter includes a control board and a radio frequency switch. The control board has at least two interfaces for a respective at least two modems and is configured to communicatively couple to at least one onboard system in a vehicle. The control board activates a selected modem interfaced to one of the at least two interfaces. The radio frequency switch is communicatively coupled to the control board via the selected one of the at least one modem. The radio frequency switch communicatively couples an antenna to the selected modem. When the control board is communicatively coupled to the at least one onboard system and activates the selected modem, and when the radio frequency switch is communicatively coupled to the antenna, the antenna is communicatively coupled to the at least one onboard system via the selected modem.
A reconfigurable wireless modem adapter is provided. The reconfigurable wireless modem adapter includes a control board and a radio frequency switch. The control board includes at least two user-data interfaces for respective at least two modems, the modems including at least one diversity/multiple-input-multiple-output (MIMO) modem. The control board is configured to communicatively couple to at least one onboard system in a vehicle and to activate one of the at least one diversity/MIMO modem interfaced to one of the at least two user-data interfaces. The radio frequency switch is communicatively coupled to the control board via a modem-select interface and the selected one of the at least one diversity/MIMO modem. The radio frequency switch communicatively couples one of at least one diversity/MIMO antenna on the vehicle to the selected one of the at least one diversity/MIMO modem based on a control signal.
The present disclosure is a novel utility of a software defined radio (SDR) based Distributed Antenna System (DAS) that is field reconfigurable and support multi-modulation schemes (modulation-independent), multi-carriers, multi-frequency bands and multi-channels. The present disclosure enables a high degree of flexibility to manage, control, enhance, facilitate the usage and performance of a distributed wireless network such as flexible simulcast, automatic traffic load-balancing, network and radio resource optimization, network calibration, autonomous/assisted commissioning, carrier pooling, automatic frequency selection, frequency carrier placement, traffic monitoring, traffic tagging, pilot beacon, etc. As a result, the SDR DAS can increase the efficiency and traffic capacity of the operators' wireless network.
A system for inserting a robot through an opening which includes a robot, the robot, payload, a tether, and a remote controller. The robot includes a first body supporting a first ground engaging drive and a second body supporting a second ground engaging drive. A pivoting connective linkage is provided between the first body and the second body. The connective linkage has an operative position in which the first body and the second body are in parallel spaced relation and an insertion position in which the first body and the second body are aligned on a common axis. An actuator is provided for moving the connective linkage from the insertion position to the operative position.
One or more physical RCDs (PRCDs) are shared between one or more workloads in one or more virtual computing environments. Example PRCD sharing operations may include: (1) providing a virtual RCD (VRCD) for one of the workloads, the VRCD being programmed with an IC design representing a hardware implementation of a software hotspot in the workload, (2) allocating one of the PRCDs to the workload by scheduling the programmed VRCD on the PRCD, (3) burning the PRCD with the IC design of the programmed VRCD so that the PRCD becomes a programmed PRCD that is capable of implementing the workload's hotspot in hardware, and (4) invoking the programmed VRCD instead of executing the hotspot as software in order to cause the programmed PRCD to implement the hotspot in hardware.
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.
Methods and systems for facilitating electronic transactions using one or more computer based devices and remote requests and authorizations for funding proposed transactions for products or services.
A system and method for operating a product return system. One or more electronic devices are received from a carrier at a return provider. A determination is made whether the one or more electronic devices include customer personal information. The one or more electronic devices are quarantined in response to determining the one or more electronic devices include CPI. The one or more electronic devices are processed in response to determining the CPI has been removed.
A secure tender electronic card for use in purchasing a service or a commodity comprises: a plastic substrate; at least two radio frequency identifications (RFIDs) embedded within the plastic substrate, the RFIDs including: a card code RFID with an identification chip having embedded therein an electronic card identification code associated with a card account file resident in a remote server, the card account file including a beneficiary code and a card usage parameter; and a tender RFID with a tender chip having embedded therein a code associated with at least some of the monetary value of the electronic card.
A system and methods for delivering targeted marketing offers to consumers during a session with an online (web-based) Internet portal, particularly suitable for online banking portals of financial institutions. An offer management system receives information corresponding to an advertising campaign of an advertiser corresponding to terms of a targeted marketing offer to be provided to a consumer accessing the online portal, and provides advertising campaign data corresponding to the targeted marketing offer and to an offer-triggering event to an offer placement system. An offer placement system receives the advertising campaign data, determines the occurrence of the offer-triggering event by a consumer during an online session with the online portal, and delivers information corresponding to the targeted marketing offer to the consumer. In response to the offer-triggering event, such as display of a list of transactions, the predetermined targeted marketing offer is delivered to the consumer during the online session.
A system for evaluating the convergence to a solution for a matrix equation comprises at least one reconfigurable computing device such as a field programmable gate array (FPGA), an update storage element, a conversion element, a summation unit, and a comparator. The FPGA includes a plurality of configurable logic elements and a plurality of configurable storage elements, which are utilized to form the update storage element, the conversion element, the summation unit, and the comparator. The update storage element is configured to store a plurality of updates. The conversion element determines the absolute value of the updates. The summation unit accumulates the absolute values of the updates to produce a total sum, which is compared to a convergence factor by the comparator. Convergence is signaled when the total sum is less than the convergence factor.
Systems and methods for product purchase and registration are disclosed. One disclosed method includes the steps of capturing a product identifier, the product identifier identifying a product; transmitting the product identifier to a first remote server; responsive to transmitting the product identifier, receiving a vendor identification number (VIN), the VIN based on the product identifier; providing the VIN to a point-of-sale (POS) device; and activating the product.
A testing device, system, and method for removing customer personal information (CPI). The testing device includes a user interface for communicating information and receiving user input. The testing device also includes interfaces operable to communicate with the one or more electronic devices. The testing device also includes a memory configured to store a libraries providing information for removing CPI from electronic devices including a number of makes, models, and configurations. The testing device also includes logic operable to utilize the libraries to analyze CPI included on the one or more electronic devices, record an identification of the one or more electronic devices in response to determining the CPI is present on the one or more electronic devices, remove the CPI from the one or more electronic devices in response to determining the CPI is present on the one or more electronic devices, and report the identification and CPI information of the one or more electronic devices in response to determining the CPI was present on the one or more electronic devices.
VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. The VLSI layouts with spacial locality exploitation presented are applicable to generalized multi-stage and pyramid networks, generalized folded multi-stage and pyramid networks, generalized butterfly fat tree and pyramid networks, generalized multi-link multi-stage and pyramid networks, generalized folded multi-link multi-stage and pyramid networks, generalized multi-link butterfly fat tree and pyramid networks, generalized hypercube networks, and generalized cube connected cycles networks for speedup of s.gtoreq.1. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.
In accordance with the invention, VLSI layouts of generalized multi-stage networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation. The VLSI layouts presented are applicable to generalized multi-stage networks V(N.sub.1, N.sub.2, d, s), generalized folded multi-stage networks V.sub.fold(N.sub.1, N.sub.2, d, s), generalized butterfly fat tree networks V.sub.bft(N.sub.1, N.sub.2, d, s), generalized multi-link multi-stage networks V.sub.mlink(N.sub.1, N.sub.2, d, s), generalized folded multi-link multi-stage networks V.sub.fold-mlink(N.sub.1, N.sub.2, d, s), generalized multi-link butterfly fat tree networks V.sub.mlink-bft(N.sub.1, N.sub.2, d, s), and generalized hypercube networks V.sub.hcube(N.sub.1, N.sub.2, d, s) for s=1, 2, 3 or any number in general. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.
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