This paper describes an embedded FFT processor where the higher radices butterflies maintain one complexmultiplier in its critical\npath. Based on the concept of a radix-r fast Fourier factorization and based on the FFT parallel processing, we introduce a new\nconcept of a radix-r Fast Fourier Transform in which the concept of the radix-r butterfly computation has been formulated as the\ncombination of radix-2????/4???? butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices\nwould be feasible since itmaintains approximately the same complexity of the radix-2/4 butterflywhich is obtained by block building\nof the radix-2/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2/4 module\nthat is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2/4 module.
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