New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis\nof a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive\ndifferent analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by\nthe proposed ternary half and full adders consumes 2.33 ????Wless power than the one implemented by the previous adder cells. It is\nalmost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors\nare used to form the novel circuits, which are entirely suitable for practical applications.
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