Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design\ncriteria for integrated circuits, A 10 Ã?â?? 10 Jacobi Brent-Luk-EVD array with the simplified ????-CORDIC processor is used as an\nexample.Thee xperimental results show that using the ????-CORDIC processor is beneficial for the design criteria as it yields a smaller\narea, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that\nthe proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing\nbeamforming or DOA estimation.
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