Being an essential part of infrared readout integrated circuit, correlated double sampling (CDS) circuits play important roles in both\ndepressing reset noise and conditioning integration signals. To adapt applications for focal planes of large format and high density,\na new structure of CDS circuit occupying small layout area is proposed, whose power dissipation has been optimized by using\nMOSFETs in operation of subthreshold region, which leads to 720 nW. Then the noise calculation model is established, based on\nwhich the noise analysis has been carried out by the approaches of transfer function and numerical simulations using SIMULINK\nand Verilog-A. The results are in good agreement, demonstrating the validity of the present noise calculation model. Thermal noise\nplays a dominant role in the long wave situation while 1/f noise is themajority in the medium wave situation. The total noise of\nlong wave is smaller than medium wave, both of which increase with the integration capacitor and integration time increasing.
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