Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects\non chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate\npower consumption but also introduce spurious switching activities in the combinational logic. In this paper, we propose a novel\narea-efficient gating scan architecture that offers an integrated solution for reducing total average power in both scan cells and\ncombinational part during shift mode. In the proposed gating scan structure, conventional master/slave scan flip-flop has been\nmodified into a new gating scan cell augmented with state preserving and gating logic that enables average power reduction in\ncombinational logic during shift mode.The new gating scan cells also mitigate the number of transitions during shift and capture\ncycles. Thus, it contributes to average power reduction inside the scan cell during scan shifting with low impact on peak power\nduring capture cycle. Simulation results have shown that the proposed gating scan cell saves 28.17%total average power compared to\nconventional scan cell that has no gating logic and up to 44.79% compared to one of the most common existing gating architectures.
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