With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers\n(LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP)\noptimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise\nobserved in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried\nout to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length\nmodulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently\ncalculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex\noptimization are detailed.The method is applied to the design of inductive source degenerated common source amplifiers at the\n90nm and 180nm technology nodes. The optimization results are validated through comparison with numerical simulations using\nAgilent�s Advanced Design Systems (ADS) software.
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