The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB\nmirror full adder is implemented by using a commercial 45nm bulk CMOS triple-well technology and compared to equivalent\nconventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running\nconditions. Post layout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a\nsignificant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS\napproaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but\nit is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high\nlevel of robustness against temperature fluctuations and process variations.
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