This paper proposes FuMicro, a fused microarchitecture integrating both in-order superscalar and Very Long Instruction Word\n(VLIW) in a single core. A processor with FuMicro microarchitecture can work under alternative in-order superscalar and VLIW\nmode, using the same pipeline and the same Instruction Set Architecture (ISA). Small modification to the compiler is made to\nexpand the register file in VLIW mode.The decision of mode switch is made by software, and this does not need extra hardware.\nVLIW code can be exploited in the form of library function and the users will be exposed under only superscalar mode; by this\nmeans,we can provide the users with a convenient development environment. FuMicro could serve as a universal microarchitecture\nfor it can be applied to different ISAs. In this paper, we focus on the implementation of FuMicro with ARM ISA. This architecture\nis evaluated on gem5, which is a cycle accurate microarchitecture simulation platform. By adopting FuMicro microarchitecture,\nthe performance can be improved on an average of 10%, with the best performance improvement being 47.3%, compared with that\nunder pure in-order super scalar mode. The result shows that FuMicro microarchitecture can improve Instruction Level Parallelism\n(ILP) significantly, making it promising to expand digital signal processing capability on a General Purpose Processor.
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