Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to\nthe detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature\nto find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of\nan error in the output of a circuit.These critical gates should be hardened first under the area constraint of design criteria. Indeed,\noutput bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors.The\n74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach.
Loading....