This paper presents an implementation of comparator (1-bit)\ncircuit using a MUX-6T based adder cell. MUX-6T full adder cell is\ndesigned with a combination of multiplexing control input and Boolean\nidentities. The proposed comparator design features higher computing\nspeed and lower energy consumption due to the efficient MUX-6T adder\ncell. The design adopts multiplexing technique with control input to\nalleviate the threshold voltage loss problem which is commonly\nencountered in Pass Transistor Logic (PTL) design. The proposed design\nsuccessfully embeds the buffering circuit in the full adder design which\nhelps the cell to operate at lower supply voltage compared with the other\nrelated existing designs. It also enhances the speed of the cascaded\noperation significantly while maintaining the performance edge in energy\nconsumption. In the proposed design, the transistor count is minimized. For\nperformance comparison, the proposed MUX-6T comparator (1-bit) is\ncompared with four existing full adders based comparators using BSIM4\nmodel parameters. The simulations are performed for 65nm process models\nindicate that the proposed design has lowest energy consumption along\nwith the performance edge in both speed and energy consumption. The\nvariants namely area and power of the proposed comparator is also\ncompared with the published author designs to validate its suitability for\nlow power and high speed mobile communication applications.
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