Multiplier is one of the essential component in the digital world such as in digital\nsignal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due\nto the complexity of the multiplier, tendency of errors are very high. This paper aimed to design\na 2x2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption\nand high performance. This design have been implemented using 90nm Complemetary Metal\nOxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA)\nTools. Implementation of the multiplier architecture is by using the reversible logic gates. The\nfault tolerance multiplier used the combination of three reversible logic gate which are Double\nFeynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of\n160�¼m x 420.3�¼m (67.25 mm�²). This design achieved a low power consumption of 122.85�¼W\nand propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power\nconsumption and high performance which suitable for application of modern computing as it has\na fault tolerance capabilities.
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