3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC)\ntopologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely\nto include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlockfree\nrouting and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections,\ncommonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several\nalternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed\nsolution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators,\nand a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by\nsimulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results\ndemonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.
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