This paper presents a new quenching circuit (QC) and single photon avalanche diode\n(SPAD) implemented in TSMC CMOS 65 nm technology. The QC was optimized for single photon\ntiming resolution (SPTR) with a view to an implementation in a 3D digital SiPM. The presented QC\nhas a timing jitter of 4 ps full width at half maximum (FWHM) and the SPAD and QC has a 7.8 ps\nFWHM SPTR. The QC adjustable threshold allows timing resolution optimization as well as SPAD\nexcess voltage and rise time characterization. The adjustable threshold, hold-off and recharge are\nessential to optimize the performances of each SPAD. This paper also provides a better understanding\nof the different contributions to the SPTR. A study of the contribution of the SPAD excess voltage\nvariation combined to the QC time propagation delay variation is presented. The proposed SPAD\nand QC eliminates the SPAD excess voltage contribution to the SPTR for excess voltage higher than\n1 V due to its fixed time propagation delay.
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