This paper proposes a restricted coulomb energy neural network (RCE-NN) with an\nimproved learning algorithm and presents the hardware architecture design and VLSI implementation\nresults. The learning algorithm of the existing RCE-NN applies an inefficient radius adjustment,\nsuch as learning all neurons at the same radius or reducing the radius excessively in the learning\nprocess. Moreover, since the reliability of eliminating unnecessary neurons is estimated without\nconsidering the activation region of each neuron, it is inaccurate and leaves unnecessary neurons\nextant. To overcome this problem, the proposed learning algorithm divides each neuron region in\nthe learning process and measures the reliability with different factors for each region. In addition,\nit applies a process of gradual radius reduction by a pre-defined reduction rate. In performance\nevaluations using two datasets, RCE-NN with the proposed learning algorithm showed high\nrecognition accuracy with fewer neurons compared to existing RCE-NNs. The proposed RCE-NN\nprocessor was implemented with 197.8K logic gates in 0.535 mm2 using a 55 nm CMOS process and\noperated at the clock frequency of 150 MHz.
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