The power consumption is an important factor in communication and embedded system applications. The power consumption of any device can be reduced, only when there is reduction in static and dynamic power consumption .The performance of the circuit is also degraded due to minimising the power supply requirement. This paper reports on the design of a phase-locked-loop (PLL) for on-chip clock generation for a high-performance application. The power consumption of the applications has been reduced by scaling down the supply voltage. The whole system has been implemented using a 1.25um CMOS process that features low-threshold voltages for MOS devices to maintain the speed performance.
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