The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking\r\nCMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a\r\ntiming optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization flow for mixedstatic-\r\ndynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and\r\nInternational Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an\r\naverage improvement in delay by 38% and delay uncertainty from process variations by 35% in comparison with a state-of-the-art\r\ncommercial optimization tool.
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