A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT)\r\nmodulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g.\r\nThe paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and\r\nread address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition,\r\nthe complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and\r\nmultipliers are avoided. Using 0.13um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07mm2, and\r\nthe synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar\r\nworks with respect to hardware complexity and max frequency while maintaining high flexibility.
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