This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for
multiple industrial protocols and compatible with different protocol versions. Targeting a wide
operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator
(VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization
scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several
bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feedforward
equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization.
The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied
an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of
0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane’s data
rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate
and can tune an equalization up to 10 dB.
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