This paper presents a 10 bit 100 MS/s asynchronous successive approximation register
(SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS)
applications. Several techniques are adopted in the proposed switching procedure to achieve better
linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number
of capacitors; a parallel split capacitor array in combination with a partially thermometer coded
technique can minimize the switching energy, improve speed, and decrease differential non-linearity
(DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the
asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active
area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of
51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured
DNL and integral non-linearity (INL) without calibration are +0.37/0.44 and +0.48/0.63 LSB,
respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of
merit (FoM) of 35.6 fJ/conversion-step.
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