,is research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. ,e operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). ,enovel design consumes a DC power of 2.1mW, poweradded efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. ,e simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.
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