The paper presents a unified hybrid architecture to compute the 8 Ã?â?? 8 integer inverse discrete cosine transform (IDCT) of\r\nmultiple modern video codecsââ?¬â?AVS, H.264/AVC, VC-1, and HEVC (under development). Based on the symmetric structure\r\nof the matrices and the similarity in matrix operation, we develop a generalized ââ?¬Å?decompose and shareââ?¬Â algorithm to compute the\r\n8 Ã?â?? 8 IDCT. The algorithm is later applied to four video standards. The hardware-share approach ensures the maximum circuit\r\nreuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly.\r\nThe design is implemented on FPGA and later synthesized in CMOS 0.18um technology. The results meet the requirements of\r\nadvanced video coding applications
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