The performance of Digital PLL is primarily dependent on the lock time, it is the time the PLL takes to adapt and settle after a sudden change of the input signal frequency. It is desired to design a fast locking DPLL. The high speed throughput applications needed for information technology demand that the lock time should be as small as possible. Fast locking is also of great importance for fast frequency hopping among data bursts in high-speed digital communications. The fast locking DPLL proposed in this paper contains two main stages of tunings the wide frequency range, as a coarse stage and fine stage. The DPLL design implemented on Advance Design System Tool in 0.18μm CMOS process using BSIM3 model and can operate from 200MHz to 1.8 GHz with 3.3V power supply. The main aim of the work is to enhance the performance of DPLL by reducing the lock time below 100 nsec for wider RF rage and to achieve a high degree of accuracy in the work. Thus, it can reduce the design complexity as well as locking time of the DPLL, making it very proper design for system-on-chip applications.
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