The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient\r\nway of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan\r\nchain. In this paper, we propose a graph-based approach to a stitching algorithm for automatic and optimal scan chain insertion\r\nat the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity\r\ninformation from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem\r\nto determine the best scan-stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis\r\nand implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.
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