This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular\r\nredundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with\r\nthe simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller\r\nRCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving\r\nand gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation\r\nand experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best\r\ndelay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the\r\napproach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI\r\nimplementation makes this proposed approach attractive for ASIC designs.
Loading....