Thescaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is nowapproaching\nits limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was\ninvented to overcome the problem by allowing transistors to be scaled down into sub-20nm region. In this work, the FinFET\nstructure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold\nregion for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG),\nand Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against\nconventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-\nCommonMulti-Gate (BSIM-CMG) 16nmlowpower libraries are used. Propagation delay, average power dissipation, power-delayproduct\n(PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The\n1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and\nEDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance\nand good current driving capabilities
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