This paper proposes a review on various methods employed to design Asynchronous viterbi decoder for low power consumption. It also focuses on the comparative study of synchronous and asynchronous low power design methodologies ranging from System level to Layout level are presented. The paper describes the various decoding techniques used for reducing the switching activity by avoiding unnecessary Memory operations. It also states the Protocols used for asynchronous viterbi decoder to synchronize and communicate the various units of viterbi decoder and to reduce power dissipation.
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