This paper presents a new hardware reconfiguration approach named hardware reconfiguration
through digital television (HARD), which can update FPGA hardware modules based
on digital TV (DTV) signals. Such a scheme allows several synthesized hardware cores (bitstreams)
signaled and broadcast through open DTV signals via data streaming to be identified, acquired,
decoded, and then used for system updates. Reconfiguration data are partitioned, encapsulated into
private sections, and then sent in a carrousel fashion in order to be recovered by modified receivers.
Service information content, specially designed for identifying and describing the characteristics of
multiplexed hardware bitstreams, was added to the transmitted signal and provided all necessary
information in the traditional DTV style. The receiver framework, in turn, checked whether those
characteristics corresponded to its embedded reconfigurable devices and, if a match was found, it
reassembled the related bitstreams and reconfigured the respective internal circuits. Experiments
performed with an implementation of the proposed methodology confirmed its feasibility and
showed that remounting and reconfiguration times were satisfactory and presented no blocking
aspect. Finally, HARD can be used in several designs regarding intelligent reconfigurable devices,
minimize device costs in the long term, and provide better hardware reuse.
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