A readout integrated circuit (ROIC) using two-step fastest signal identification (FSI)\nis proposed to reduce the number of input channels of a data acquisition (DAQ) block with a\nhigh-channel reduction ratio. The two-step FSI enables the proposed ROIC to filter out useless input\nsignals that arise from scattering and electrical noise without using complex and bulky circuits.\nIn addition, an asynchronous fastest signal identifier and a self-trimmed comparator are proposed\nto identify the fastest signal without using a high-frequency clock and to reduce misidentification,\nrespectively. The channel reduction ratio of the proposed ROIC is 16:1 and can be extended to\n16 Ã?â?? N:1 using N ROICs. To verify the performance of the two-step FSI, the proposed ROIC was\nimplemented into a gamma photon detector module using a Geiger-mode avalanche photodiode\nwith a lutetium-yttrium oxyorthosilicate array. The measured minimum detectable time is 1 ns.\nThe difference of the measured energy and timing resolution between with and without the two-step\nFSI are 0.8% and 0.2 ns, respectively, which are negligibly small. These measurement results show\nthat the proposed ROIC using the two-step FSI reduces the number of input channels of the DAQ\nblock without sacrificing the performance of the positron emission tomography (PET) systems.
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