This paper describes a novel energy-efficient, high-speed ADC architecture\ncombining a flash ADC and a TDC. A high conversion rate can be obtained\nowing to the flash coarse ADC, and low-power dissipation can be attained\nusing the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is\nproposed to achieve high linearity. A test chip was fabricated using 65-nm\ndigital CMOS technology. The test chip demonstrated a high sampling frequency\nof 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low\nFOM of 32 fJ/conversion-step.
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