An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-\nOxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ)\ndevices are added on top of a conventional D flip-flop for temporary storage during the power-down.\nAn area overhead of the temporary storage is minimized by reusing a part of the D flip-flop\nand an energy overhead is reduced by a current-reuse technique. In addition, two optimization\nstrategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design\nphase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for\nreducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model\ntargeting an implementation in a 10 nm technology node. Results indicate that area overhead is\n6.9% normalized to the conventional flip flop. Compared to the best previously known NVFFs,\nthe proposed circuit succeeded in reducing the area by 4.1* and the energy by 1.5*. The proposed\nplacement strategy of the NVFF shows an improvement of nearly a factor of 2-18 in terms of area\nand energy, and the pulse duration modulation provides a further energy reduction depending on\nfault tolerance of programs.
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