This paper proposes a 16 bit subthreshold adder design using bootstrapped sense\namplifier-based pass transistor logic (bootstrapped SAPTL) to overcome serious performance\ndegradation and enhance the immunity to process variations in the subthreshold region.\nThrough employing a bootstrapped sense amplifier including a voltage boosting part and adopting\nan adder architecture based on bootstrapped SAPTL, significant improvements in performance\nand energy efficiency can be achieved. A case study of 16 bit adders in SMIC 130 nm technology\ndemonstrated that the proposed adder outperformed other works in terms of performance, energy\nconsumption, and energy efficiency. Furthermore, the statistical results of the Monte Carlo analysis\nproved the proposed adderâ??s significant enhancement of robustness against process and temperature\nvariations. At 0.3 V (TT corner, 25 DegreeC), the proposed 16 bit adder achieved improvements of 72% in\nperformance and 8% in energy savings, as well as a 74% reduction in energy-delay production as\ncompared with the current design.
Loading....