Poly-crystalline silicon channel transistors have been used as a display TFT for a long time\nand have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND\nupright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has\nbeen used to suppress the short-channel effects for logic/analog and memory applications. Compact\nmodels for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon\nchannel GAA MOSFETs have been developed separately, however, there are few models consider\nthese two physics at the same time. In this work, we derived new analytical current-voltage model\nfor GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain\nboundary effect. Based on the derived formula, the compact I-V model for various operating regions\nand threshold voltage was proposed for the first time. The proposed model was compared with the\nmeasured data and good agreements were observed.
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