The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or\r\nthousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on\r\nthe chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection\r\nbackbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture\r\nbecomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a\r\npromising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip\r\ncommunications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal\r\nwell with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC.\r\nFinally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed\r\nto break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.
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