Apower efficient circuit topology is proposed to implement a low-voltageCMOS 2-input pass-transistorXOR gate. This design aims\r\nto minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate\r\nutilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nmIBMCMOS process.Theperformance\r\nof the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The\r\narea of the core circuit is only about 56 sq �· ??m with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8V supply\r\nvoltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.
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