Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is\r\npresented in this paper with the aimof reaching high efficiency.Themidoutputs are obtained fromaMulti-output dynamic module.\r\nThen, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also\r\nsurveyed and compared in the paper. All circuits are simulated by HSPICE with 32 nm CNFET technology. The proposed design\r\nis the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most\r\nhigh-performance cell, which is DDCVS.
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