Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness (??SI) ranging from 46 nm\r\n(UTB scale) down to 1.6nm (NSB scale), were fabricated using a selective ââ?¬Å?gate recessedââ?¬Â process on the same silicon wafer. The\r\ngate-to-channel capacitance (????) and conductance (????) complementary characteristics, measured for NSB devices, were found to\r\nbe radically different from those measured for UTBS. Consistent ???? and ???? trends are observed by varying the frequency (??), the\r\nchannel length (??), and the channel thickness (??SI). In this paper, we show that these trends can be analyticallymodeled by amassive\r\nseries resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap\r\ndensity are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in\r\nwhich series resistance is of a great concern.
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