We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a\r\nprogrammable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can\r\nstore 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write\r\npulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required\r\nwhen using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell\r\nbefore the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we\r\nsimulated the effect of variations in the width of the transistor of the proposedMNV-SRAMcell, the resistance of the programmable\r\nresistor, and the power supply voltage with 180nm 3.3V CMOS HSPICE device models.
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