Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based\non various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream\nelectronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of\noptimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle\nswarmoptimization (DPSO) algorithmwas applied to optimize the timing of themixed polarityReed-Muller (MPRM) logic circuit.\nSecond, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special\nsettings and constraints. Finally, the timing optimization results of the two algorithms were compared based onMCNC benchmark\ncircuits.Thetiming optimization results obtained usingDPSOare comparedwith those obtained fromDC, andDPSOdemonstrates\nan average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed\nverification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.
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