The development of modern networking requires that high-performance network\nprocessors be designed quickly and efficiently to support new protocols. As a very important\npart of the processor, the parser parses the headers of the packetsâ??this is the precondition for\nfurther processing and finally forwarding these packets. This paper presents a framework designed\nto transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays\n(FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler.\nThe hardware architecture comprises many components with varying functionality, each of which\nhas its own optimized VHDL template. By using the output of a standard frontend P4 compiler,\nour proposed compiler extracts the parameters and relationships from within the used components,\nwhich can then be mapped to corresponding templates by configuring, optimizing, and instantiating\nthem. Finally, these templates are connected to output VHDL code. When a prototype of this\nframework is implemented and evaluated, the results demonstrate that the throughputs of the\ngenerated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with\nstate-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when\nsimilar amounts of resources are being used.
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