In this article we present an ASIP design for a discrete fourier transform (DFT)/discrete cosine transform (DCT)/finite\r\nimpulse response filters (FIR) engine. The engine is intended for use in an accelerator-chain implementation of\r\nwireless communication systems. The engine offers a very high degree of flexibility, accepting and accelerating\r\nperformance approaches that of any-number DFT and inverse discrete fourier transform, one and two dimension\r\nDCT, and even general implementations of FIR equations. Performance approaches that of dedicated\r\nimplementations of such algorithms. A customized yet flexible redundant memory map allows processor-like\r\naccess while maintaining the pipeline full in a dedicated architecture-like manner. The engine is supported by a\r\nproprietary software tool that automatically sets the rounding pattern for the accelerator rounder to maintain a\r\nrequired signal to quantization noise or output RMS for any given algorithm. Programming of the processor is\r\ndone through a mid-level language that combines register-specific instructions with DFT/DCT/FIR specificinstructions.\r\nOverall the engine allows users to program a very wide range of applications with software-like ease,\r\nwhile delivering performance very close to hardware. This puts the engine in an excellent spot in the current\r\nwireless communications environment with its profusion of multi-mode and emerging standards
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