Exploiting the Bachet weight decomposition theorem, a new two-dimensional filter is\ndesigned. The filter can be adapted to different multimedia applications, but in this work it is\nspecifically targeted to image processing applications. The method allows emulating standard\n32 bit floating point multipliers using a chain of fixed point adders and a logic unit to manage the\nexponent, in order to obtain IEEE-754 compliant results. The proposed design allows more compact\nimplementation of a floating point filtering architecture when a fixed set of coefficients and a fixed\nrange of input values are used. The elaboration of the data proceeds in raster-scan order and is capable\nof directly processing the data coming from the acquisition source thanks to a careful organization of\nthe memories, avoiding the implementation of frame buffers or any aligning circuitry. The proposed\narchitecture shows state-of-the-art performances in terms of critical path delay, obtaining a critical\npath delay of 4.7 ns when implemented on a Xilinx Virtex 7 FPGA board.
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