There is a growing need in computer vision applications for stereopsis, requiring not only accurate distance but\r\nalso fast and compact physical implementation. Global energy minimization techniques provide remarkably precise\r\nresults. But they suffer from huge computational complexity. One of the main challenges is to parallelize the\r\niterative computation, solving the memory access problem between the big external memory and the massive\r\nprocessors. Remarkable memory saving can be obtained with our memory reduction scheme, and our new\r\narchitecture is a systolic array. If we expand it into N�s multiple chips in a cascaded manner, we can cope with\r\nvarious ranges of image resolutions. We have realized it using the FPGA technology. Our architecture records 19\r\ntimes smaller memory than the global minimization technique, which is a principal step toward real-time chip\r\nimplementation of the various iterative image processing algorithms with tiny and distributed memory resources\r\nlike optical flow, image restoration, etc.
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