This paper examines the implementation of a retinal vessel tree extraction technique on different hardware\r\nplatforms and architectures. Retinal vessel tree extraction is a representative application of those found in the\r\ndomain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of lowlevel\r\ntasks in order to meet the accuracy requirements. In some applications, this might compromise computing\r\nspeed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on\r\ndifferent hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively\r\nparallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate\r\narrays (FPGA).
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