This paper describes a hardware architecture for real-time image component labeling and the computation of image component\nfeature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine\nvision systems demand a robust performance and power efficiency as well as minimum area utilization, depending on the deployed\napplication. In the proposed architecture, the hardware modules for component labeling and feature calculation run in parallel.\nA CMOS image sensor (MT9V032), operating at a maximum clock frequency of 27MHz, was used to capture the images. The\narchitecture was synthesized and implemented on a Xilinx Spartan-6 FPGA. The developed architecture is capable of processing\n390 video frames per second of size 640 Ã?â?? 480 pixels. Dynamic power consumption is 13mWat 86 frames per second.
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