Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The\r\ndesign methodology is illustrated with a 640 MS/s, 20MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 ??m\r\nCMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming\r\nonly 19.7mW from 1.8V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one\r\nclock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra\r\nsummation opamp.
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