Frequency: Quarterly E- ISSN: 2230-8202 P- ISSN: 2249-135X Abstracted/ Indexed in: Ulrich's International Periodical Directory, Google Scholar, Genamics JournalSeek, JOURNAL directory, getCITED, EBSCO Information Services
Quarterly published in print and online "Inventi Impact: VLSI" publishes high quality unpublished as well as high impact pre-published research and reviews catering to the needs of researchers and professionals. The journal covers all recent advances in very large scale integration. The focus areas are: VLSI circuits; low power and power-aware designs; testing, reliability & fault-tolerance; emerging technologies; VLSI applications; nano electronics, molecular, biological and quantum computing; and, wireless communications.
In the IoT/wearable devices, the antenna is shared with the receiver and transmitter of the\ntransceiver. This requires the control of the switch between the antenna and the control circuitry to\nachieve both low insertion loss and high isolation. This paper presents a low insertion loss and high\nisolation switch based on Single Pole Double Throw (SPDT) switch for 2.4 GHz Bluetooth low power\n(BLE) transceiver. The body-floating technique is used to improve the insertion lossâ??s performance.\nAn ultra-small on-chip matching network with high Q-factor is proposed. The shunt transistors\nare used as active shunt capacitors that create the active matching network to improve isolation\ncharacteristics. The proposed SDPT switch was designed using 55 nm CMOS process with the total....................
This paper presents a small-size broadband slot monopole chip antenna for millimeter wave application. Using a 0.18 μm CMOS process, through metal_1, the artificial magnetic conductor (AMC) of the metal layer increased the impedance bandwidth of the chip antenna. The additional inverted C branch was used to achieve a better reflection coefficient. By adding an AMC and inverted C branch, the operating frequency of the chip antenna went to 33.8–110 GHz below the reflection coefficient of −10 dB, and its fractional bandwidth was 103.4%. The maximum gain was −6.3 dBi at 72 GHz. The overall chip size was 1.2 × 1.2 (mm2). Through measurement and verification, the proposed antenna reflection coefficient was close to the simulation trend and had better resonance. The frequency range of the chip antenna proposed in this paper covered the 5G NR FR2 band (24.2 GHz–52.6 GHz) and W-band (75 GHz–110 GHz). The proposed chip antenna can be applied to the Internet of Things, Industry 4.0, biomedical electronics, near field sensing and other related fields....
This paper presents the design, fabrication, and electrical characterization of an\nelectrostatically actuated and capacitive sensed...plate resonator structure that exhibits a\npredicted mass sensitivity of.... The resonator is embedded in a fully on-chip\nPierce oscillator scheme, thus obtaining a quasi-digital output sensor with a short-term frequency\nstability of....(...) n air conditions, corresponding to an equivalent mass noise floor as\nlow as.... The monolithic CMOS-MEMS sensor device is fabricated using a commercial..... metal complementary metal-oxide-semiconductor (CMOS) process, thus featuring\nlow cost, batch production, fast turnaround time, and an easy platform for prototyping distributed\nmass sensors with unprecedented mass resolution for this kind of devices....
Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/ read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2....
This paper presents an electrochemical impedance spectroscopy (EIS) system-on-chip in 0.18-μm CMOS, achieving a wide scan frequency range of 1.25 MHz. An on-chip direct digital frequency synthesizer generates a digital sine wave as well as in-phase and quadrature-phase clocks that are synchronized to the sinewave. A chopped sampling mixer realizes lock-in detection without requiring quadrature sinewaves while suppressing low-frequency noise and offset. The receive utilizes a 12-bit pipelined SAR ADC operating in 5 MS/s in combination with a digital averaging filter to maximize the dynamic range. The measured performance shows that the prototype EIS chip achieves the highest frequency scan range with a comparable dynamic range of 108 dB and power consumption of 14 mW when compared with the previous state-of-the-art prototypes....
This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feedforward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane’s data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB....
This article describes an asynchronous split-CDAC-based SAR ADC with integrated input PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage, avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes, the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s....
This brief presents an analog front-end (AFE) for the detection of electroencephalogram (EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency. The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage. The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology. The overall power consumption is approximately 13 μW, achieving ultra-low-power operation....
This paper presents a differential 19.6–39.4 GHz broadband low-noise amplifier (LNA) in 65-nm CMOS technology. The LNA consists of two cascode stage and one common-source stage. To achieve a wide bandwidth and low average noise figure, inter-stage peak-gain distribution technique and transformer-based triple-coupled technique are developed. Besides, a new compact T-coil-based network is proposed to neutralize the parasitic capacitors and enlarge the gain. The measure results show that the 3-dB bandwidth is from 19.6 to 39.4 GHz, the maximum gain is 23.5 dB, and the noise figure (NF) is from 3.7 to 5.8 dB. The dc power comsumption is 46 mW with 1V supply voltage. The input P1dB is −17 dBm at 30 GHz....
This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process...........................
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